Modeling of the transient response of substrate traps to ... - IEEE Xplore

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO. 3, MARCH 1993

47 1

Modeling of the Transient Response of Substrate Traps to the Substrate Voltage in GaAs FET’s Nouredine Sengouga and Brian K. Jones, Member, IEEE

Abstract-The transient response of hole traps, related to the substrate in GaAs FET’s, following an electric pulse applied to the substrate (or back gate) is accurately modeled. The modeled transient is found to be nonexponential. Excellent agreement between the experimental data and the model is obtained. The trap filling time required for the substrate hole traps is very sensitive to the difference between the Fermi energy and the trap energy.

I. INTRODUCTION T IS a common observation that a negative voltage applied to the substrate reduces the channel current (or its conductance) [2]. This phenomenon is known as “backgating” or “sidegating” [6], [7], [ I 11, [16]. It is believed that deep traps in the substrate or near the channel-substrate interface are responsible for this effect. Therefore, identification and characterization of these traps is vital if this effect is to be eliminated, or at least reduced. These traps can cause problems in the mutual interaction between the devices in an integrated circuit. Also the traps cause low-frequency effects which produce noise and modulation in oscillators and mixers using these devices. In characterizing these traps, there is a widespread consensus for using optical techniques such as PITS (PhotoInduced Transient Spectroscopy) [4] instead of electrical techniques such as capacitance DLTS [ 121. The main argument against the use of electrical techniques is that it is very difficult to inject free carriers into the substrate because of its high resistivity. Another argument is that this material may have a large series resistance effect so that the simple depletion approximation analysis cannot be used. For the first argument, Zylberstejn et al. [25] showed that since a negative voltage applied to the substrate can have an effect on the channel conductance then electrical means can be used. They applied a pulse to the substrate, similar to the one usually applied to the gate, and produced a DLTS spectrum. However, the results were analyzed in the same fashion as in the usual DLTS; that is, the activation energy was evaluated from the peak posi-

I

Manuscript received February 26, 1992; revised August 20, 1992. N. Sengouga was supported by the Algerian Government. The review of this paper was arranged by Associate Editor M. Shur. N. Sengouga was with the School of Physics and Materials, Lancaster University, Lancaster LA1 4YB, United Kingdom. He is now with lnstitut d’Electrotechnique, Centre Universitaire de Biskra, BP447, 07000 Biskra, Algeria. B. K. Jones is with the School of Physics and Materials, Lancaster University, Lancaster LA1 4YB, United Kingdom. IEEE Log Number 9206099.

tion in the temperature spectrum. This can introduce large systematic errors since the transient is not a simple exponential because of two main factors. One is the fact that the trap density is orders of magnitude higher than that of the free carriers in the substrate and the second is the possible effect of the large series resistance of the semi-insulating (SI) substrate. Therefore, as was demonstrated by Broniatowski et al. [3], Simoen et al. [21], and Fourches [5], if the above effects are properly taken into account then electrical techniques can be used to study traps in high-resistivity materials such as SI GaAs and high-purity germanium. Another observation about some of these traps is that they show filling times comparable to their emission time constants. In previous work [18], [19] we have interpreted this symmetry by the fact that the Fermi ievel is pinned near the trap level in the substrate. Therefore, in characterizing this type of trap, all the problems mentioned above will be taken into account and the modeling of the response of traps located in the substrate to a voltage applied to the substrate will be presented in this paper. Its usefulness will be demonstrated by fitting it to the experimental data of two traps labeled H I and Ho located near the channel-substrate interface or in the substrate. It will also be shown how errors can be introduced if the normal analysis of substrate DLTS is used and how these errors can be eliminated using the present method. This paper is one of a series by the Lancaster group which discusses the properties and methods of analysis of trap effects in GaAs FET’s using a wide variety of techniques. 11. EXPERIMENTS The system that measures the DLTS rate window and the isothermal transient in the present experiments and the fitting procedure are described elsewhere in detail [8]. The device is biased at a constant drain-source current ZDs. A voltage pulse is applied to the substrate and the resulting transient in the drain-source voltage VDs(t)due to emission from the trap is measured using an A/D converter. In some experiments the gate voltage is pulsed. The transient can be studied at a constant temperature by changing the pulse bias levels or the filling time and can be used to produce the conventional DLTS rate window temperature spectrum. The times t , and t2 which define the rate window satisfy the relation t 2 / t l = 10.

0018-9383/93$03.00 0 1993 IEEE

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The experimental data of the measured transient are fitted to the developed theoretical curve. In the fitting procedure the least squares method is used, In this method the best fitting parameters are selected by minimizing the sum of the squares of the difference between the fitting curve and the experimental data. This sum is also known as the fitting quality factor Q . The specimens used are low-noise GaAs FET's type P35-1105 batch F2137, made by Plessey 3-5. The device has a recessed gate structure using doped epitaxial GaAs grown on a Cr-doped HB semi-insulating GaAs with a high-resistivity buffer layer. The buffer layer is -0.85 pm thick and the gate is -0.8 pm long. They are not typical of present commercial devices. 111. RESULTSAND DISCUSSION A . Location of H , and Ho Using DLTS Experiments Two traps, called H , and H,, are observed in a group of GaAs FET's labeled F2137. When the substrate is pulsed to produce a DLTS spectrum (SDLTS) then we notice the presence of HI and H0(Fig. 1). When the gate is pulsed (GDLTS), H I is completely absent from the spectrum while Ho can be clearly seen (Fig. 2). This is a first indication that H I is located in the SI substrate while Ho is more likely to be an interface trap near the neutral channel-SI substrate boundary. The bias dependence of SDLTS confirms this observation. In Fig. 3, SDLTS spectra are presented for different substrate biases. For example, if the bias limits are such that the region contributing to the transient is far from the interface then HI can be clearly seen while H, is completely absent (bias: -16, -10, -16 V, for example, in this bias sequence the transient is acquired on the third bias). The large trap signal H2 seen by GDLTS but not by SDLTS is located at the free surface between the gate and drain (or source) and is discussed in a separate publication [ 101.

B. Model for the Response of Substrate Traps to the Substrate Voltage In developing this model we assume that for these substrate traps the effect of the negative voltage applied to the substrate is to reduce the channel width and hence the channel-substrate interface acts like a p-n junction. This was shown for another substrate trap H3 by Jin and Jones [9] using a modified DLTS method and by more detailed I-I/ studies [20]. The interface depletion region expands into the neutral channel. It was also shown [18] that the change in the total conductance is proportional to the change in the channel width even if the effect appears in both the gated and access regions of the device. We also neglect any interface states which may exist at the channel-buffer or buffer-SI substrate interfaces. This assumption may not be true since several workers have reported the existerice of such states (see, for example, Look et al. [15]). However, it will be shown that at certain bias conditions this assumption is acceptable since the bulk traps dominate the interface states. We also assume that the

10

C

\

3 W

L T 5

3 W

LT

0

-

50

100 150 200 250 300 350 400 450

Temperature/K Fig. 1. A typical SDLTS spectrum for a device from the group F2137. The rate windows are (from left to right) 200, 100, 50, 25, and 12.5 ms. These rate windows are calculated using the usual formula for the time constant ([12], see also (A3) in the Appendix).

10

c

\

3 W

L T 5 h

3

W

I Y

50 100 150 200 250 300 350 400 450

Temperature/K Fig. 2. A typical GDLTS spectrum for a device from the group F2137. The rate windows are the same as in Fig. I

~ = 2 0 0ms

v=,o

v

-5,O.-5 V -16.-10,-16 V -1 6.0.-16 V

H,

Temperoture/K Fig. 3. The SDLTS spectrum at different substrate biases to clarify the location of H,and H,. The rate window is 200 ms.

ionized impurities have uniform profiles on both sides of the channel-substrate junction. The change in the channel width in the present experiment is due to the voltage applied to the substrate Ves, that is, Aa = -Aab (where a is the channel width and ab is the depletion region width spreading from the back interface because of the negative voltage applied to the substrate; the minus sign here is to indicate that when the depletion region spreads from the back interface and ab increases then the channel width a decreases). The time dependence of the conductance change is therefore given by 1181 AGDs(t)= -CAab(t) (1) where C is a constant.

~

SENGOUGA A N D JONES: TRANSIENT RESPONSE OF SUBSTRATE TRAPS TO THE SUBSTRATE VOLTAGE

If we assume, as discussed above, that the channelsubstrate junction can be treated as an n-p- junction then the depletion width in the channel is given by

413

Since the experimental data points are measured with reference to the last point (apparatus drift) then a term A0 has to be added to (5) to account for this and possible slow transients [8]. In this case, the conductance transient signal S ( t ) can be written as

where V,, is the back interface built-in voltage, No is the channel doping density, NA is the net density of free acceptors in the substrate which also includes the ionized parts of inactive deep levels [23], and N , ( t ) is the ionized deep levels (HI and Ho) density at a time t . Here V,, is the voltage drop across the space-charge region in the where Ai = A,!A2.The term NA/NTI f o r t > 0 is neglected substrate which may not be the same as the voltage ac- here since it is much less than unity. Fig. 4 shows that tually applied to the substrate VBs,because of a possible the change in the device conductance, following a change series resistance effect. Another reason is that there is also in the substrate voltage, consists of almost 100%transient a voltage drop in the channel side, although this is neg- due to deep levels. This is what Wager and McCamant ligible because No >> NA N , ( t ) . It was found from [23] referred to as one of the main differences between a detailed substrate ZBs ( VBs) characteristics that the series normal n-p junction and an n-SI junction. The former has resistance can be neglected [18], [20]. This is in agree- a fast response time due to the fast relaxation time in the ment with the findings of Yokoyama et al. [24]. They n material while the former has a slow response time due found that when apositive voltage is applied to the sub- to emission (or capture) from deep levels. strate then it is dropped in the neutral region of the subThis equation will be used to fit the experimental data strate and hence the series resistance is relatively large but to evaluate Ai,T ~ (i, = 1 , 2), and A,. Since V,, is included when a negative voltage is applied to the substrate most in A (a term evaluated by the fitting procedure) its knowlof it is dropped in the space-charge region in the channel- edge is not required and any possible series resistance efsubstrate interface and hence the series resistance is rel- fect is not important for the purpose of the present work. atively small. This is why, they concluded, the backgatIn the case of one trap ( H I in the present case) only one ing phenomenon occurs only when a negative voltage is trap is present and (6) reduces to applied to the substrate. In the present calculation whether the series resistance (7) is taken into account or not is not important. To demonstrate this we will use V,, instead of VBsand then show that the knowledge of V,, is not required since it does not For convenience we will refer to the present method as SRFM (Square Root Fitting Method). affect the purpose of the present work. Before presenting the results of SRFM, a few important Therefore, the time dependence of the change in the conductance can be described by an equation of the form remarks are made: 1) The transient due to H I is not a simple exponential (3) AGDs(t) = -C.\I[N, + N ; ( t ) ] as shown by the fitting in Fig. 5 . In this figure the data are fitted to an exponential function of the form A exp where C is a constant which includes the voltage. The time dependence of N f ( t ) usually has an exponen- ( - - t / ~ ) + A, and the fitting parameters are presented in tial form. In the case of the presence of more than one Table I. 2) By fitting the transient, at a constant temperature, at trap, the total ionized charge becomes the sum of the individual ionized traps, thus [ 181 different biases it was noticed that the equation developed for the substrate traps (HI and H,, (7)) does not give a good fit either when one of the two pulse bias levels is 0 V or for very large AV, (15 V) as compared to smaller pulse height (AVB = 4 V) (Fig. 6(a) and (b)). The fitting Substituting for N , ( t ) from (4) in ( 3 ) gives parameters for the two cases are shown in Tables I1 and 111. For the first case, that the fitting is not good may be due to the fact that when one of the pulse levels bias is 0 where N = 1 or 2 in the present case representing HI or V then the interface region contributes to the region where H i and H,, A = C / K , and A,! = NTi/NTI (i = 1, 2, the emission from traps takes place. Near this interface region there may exist interface states which were nenote that A ; = 1). This equation represents the theoretical time depen- glected in the modeling. If the pulse does not have 0 V as dence of the change in the conductance between the filling one of its levels then the fitting becomes much better and acceptable. For the second case it was foupd that this is and emptying substrate biases ( V,, and Vsl).

+

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO. 3 , MARCH 1993

474

I

.

.

.

.

.

.

.

.

.

T=303 Device:F2137/10 K V,=-15.0.-15

V

v,=o v

-

-

.Time (0.2 s/div)

Fig. 4. The conductance transient resulting from a pulse applied to the substrate showing 100% deep-level effects and comparable emptying and filling time constants.

T=303 K V,=-8.-4.-8

v=,o

v)

v

3

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Devicc:F2137/10 T=303 K

v)

v

z '

2

z

F

n I

x 1 c3 U

0

0

2

1

Fig. 5 . Fitting the conductance due to H,, resulting from a pulse applied to the substrate, using a single exponential of the form A exp ( - f / r ) + A, at AV, = 4 V. The fitting parameters are presented in Table 1.

(b) Fig. 6 . Comparison between fitting the conductance transient using SRFM ((7), for one trap) at a large AV, = 15 V (a) and a small AV, = 4 V (b). The fitting parameters are presented in Tables I1 and 111, respectively.

TABLE I

I

Device:F2137/10 T=345 K V,=-8,-4,-8 v

v

v=,o 318.916

2.118

3

Time/s

Time/s

0. I69

3.084

b -Data

because for a large pulse height, the trap within the large depleted region has a nonuniform distribution in addition to the possible presence of other traps such as EL2 (Fig. 2). 3) At high temperatures, the transient is made up from contributions from both HI and Ho. Therefore, two square fitting functions are needed to Obtain a good fit 'Fig' 7)- The fitting parameters for one function and two functions are given in Table IV. C. Characterization of H I A filling bias v B 2 is applied to the substrate for a long time, many filling and emptying time constants. This is necessary to ensure that all the traps are initially filled since the filling rate of this trap is comparable to the emptying rate. The decay in the drain-source voltage following a return to a quasi-equilibrium state is measured and then converted to a conductance to be fitted using (7). To optimize the experimental conditions, it is necessary to choose the bias limits ( v B 2 and V,,) so that in the

0.0

,

0.3

Time/s

Fig. 7. An example of fitting the transient made up of H , and H , following a pulse applied to the substrate using SRFM ((6) for more than one trap). The fitting parameters are presented in Table IV. TABLE I1 7(ms)

s)

A

1510.74

13.28

A,, (1O-'S)

Q

10.54

55.23

A, (10-3 S)

Q

2.459

0. I29

TABLE 111 7 (ms)

780.222

s)

A

2.442

__

475

SENGOUGA AND JONES: TRANSIENT RESPONSE OF SUBSTRATE TRAPS TO THE SUBSTRATE VOLTAGE 1 0’

TABLE 1V TI

N

(ms)

1

208.346 344.192

2

AI

(10-’S)

2.805 12.242

72

A?

(ms)

(IO-’S)

A0 (10 ’ S )

Q

15.832

3.655

2.869 3.745

3.217 0.139

10’ n

< Y

10‘

F I-

depleted region between the two limits, HI dominates and other traps are eliminated (Ho and EL2) if possible. The latter can be achieved by reducing the time scale over which the experimental data are taken as the temperature increases (the number of data points remains the same at all temperatures). This timing procedure is very useful since the time constant decreases rapidly with increasing temperature. The total sampling time is 107 so that reliable values for 7 can be obtained. The suitable bias conditions are achieved by selecting V,, = -4 V and V,, = - 8 V. The reason for this choice is as follows: a filling bias of V,, = 0 V is not desirable because it gives a greater chance for interface states to contribute to the total transient. Also, a very large equilibrium bias VB1is not desirable because some low-frequency oscillations have been observed in the same device and similar devices. Similarly, a large AV, is not suitable since the fitting is not good as shown in Fig. 6 . The temperature range was chosen to be 290-350 K to give a range of nearly three decades for the time constant (from a few seconds to a few milliseconds). The Arrhenius plot of the evaluated time constants as a function of the inverse of the temperature is shown in Fig. 8. In this plot is also presented the data plot of the rate window conductance DLTS results measured from the peak position and using the usual formula for the time constant [12] (see (A3) in the Appendix). The difference is very clear and is so large that any deep-level parameters evaluated from the conventional DLTS will be misleading in identifying the trap. If the time constant at the temperature where the peak occurs is evaluated using the new formula which allows for the nonexponential decay and assumes an equation of the form of (7) (see (A7) in the Appendix) then the Arrhenius plot will become closer to the plot of the present fitting method although the value of T is only approximate. Although the activation energy may not be significantly affected by this error, the capture cross section definitely is, and the process of identifying the trap will be misleading. The data of Fig. 8 are compared with those found in the literature. It was very difficult to find any reported trap for which the parameters are close to those evaluated in the conventional way from the SDLTS spectrum. For the Square Root Fitting Method (SRFM), however, the evaluated parameters are very close to the trap labeled “B” [13], [14] and “HB2” [17]. From the SRFM the evaluated activation energy is AE = 0.71 k 0.01 1 eV and the capture cross section is U,, = 5.5 x cm’. The values given by the references cited are 0.71-0.72 eV for AE and 0.58-1.2 X cm2 for up. In these references,

-

1o’

2.5

r’/l O-’K-’ 3.5

3.0

4.0

Fig. 8. The Arrhenius plot of the corrected time constant of H , evaluated by SRFM (7) (circles) versus 1 / T to evaluate the trap activation energy and capture cross section. Also shown are the Arrhenius plots of the corrected time constant evaluated from DLTS using the well-known formula for the time constant ((A3) in the Appendix) (squares), and using the new one ((A7) in the Appendix) (stars). The solid lines are the closest traps to H , reported in the literature.

capacitance DLTS techniques were used to identify these traps in GaAs p-n junctions where the density of these traps is very small compared to that of free carriers. Although this trap is usually characterized in epitaxial layers (i.e., in the references quoted above), it was not possible to attribute any of these traps to any chemical impurity. It was suggested that they might be native defects or unknown unavoidable impurities during growth such as Si or C [14]. Therefore, our conclusion that this trap is located in the SI substrate bulk is very acceptable since it might be a native defect.

D. Characterization of Ho This trap is observed in both GDLTS and SDLTS spectra. Therefore, it will be characterized by applying pulses to either the substrate or the gate before comparing the results obtained by these methods. 1 ) Substrate Pulsing (SRFM): To optimize the bias conditions for characterizing H,, the bias dependence of its amplitude was studied. It was found that the transient due to Ho dominates the transients due to other traps when the depletion region involved in the transient is nearer to the channel-substrate interface. However, the transient then has a complicated shape and it is very difficult to obtain a good fit to it. The reason for this complicated shape is the presence of some surface states and an electron-like trap (EL2) which has a comparable time constant with Ho. So a filling bias VE2= 0 V is not desirable. If a bias of V,, = - 8, -4, - 8 V is used to pulse the substrate then the two traps HI and Ho have comparable amplitudes but well separated time constants so the multi-exponential fitting of SRFM (6) should be able to separate the two traps (Fig. 7). A filling bias V,, = -4 V is applied to the substrate for a long time (many time constants); this is necessary since the filling rate of hole-like traps is comparable to the emptying rate (for HI). The substrate bias is then changed to V,, = - 8 V and the transient in VDsis mea-

IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 40, NO. 3, MARCH 1993

416

0.4

Va=-2.3.-0.8,-2.3

V

v) 0.3

b 7

\

-

U - 0.2

I

v c

19

U 0.1

0.0 0.0

0.2

0.1

0.3

0.4

0.5

Time/s Fig. 9. An MEFM example of the transient following a pulse applied to the gate to evaluate the time constant of Hoand other traps contributing to the transient. The fitting parameters are presented in Table V.

TABLE V

N r , (ms) A , 2 94.045 3 275.918

S) 0.18 0.096

T~

(ms) A 2

3.348 49.219

S) 0.15 0.125

sured at different temperatures ranging from 320 to 390 K. These transients are then converted to conductance transients and fitted using SRFM, (6). The Arrhenius plot will be presented later since it will be compared with that of GDLTS. 2) Gate Pulsing: In GDLTS the method called MEFM (Multi Exponential Fitting Method) developed in this laboratory by Jin and Jones [8] is used. In this method, the transient, following a gate pulse which is made up of several components, is decomposed to its simple exponential components. Simple exponentials are used here since the normalized conductance transient to the total conductance is only - 5 % . In characterizing this trap (Ho)by GDLTS the influence of other traps has to be minimized. This is achieved by optimizing the experimental conditions. One of these conditions is to optimize the bias levels. In this respect, a filling bias VG2= 0 V is not desirable since in this case it was observed that the trap labeled H2 (related to the free surface, [9]) dominates the total transient (Fig. 2) leading to a complicated shape of the transient. A large reverse bias is also not desirable because it gives a bigger chance for a slower trap labeled HHTin Fig. 2 to contribute to the total transient. By studying the bias dependence of the transient at a fixed temperature ( - 370 K) the optimum bias was selected as VGs = -1.3, -0.5, -1.3 V (VBs = 0 V). At this fixed bias condition, the transient in the sourcedrain voltage V,, is measured at several fixed temperatures ranging from 340 to 400 K. These transients are then converted to conductance transients and fitted to a sum of exponential components. At least three exponential components were needed to obtain a good fit to the experimental data (Fig. 9). The fitting parameters are shown in Table V.

73 (ms)

2.239

S) A , (lO-’S)

A,

0.153

-0.008 0.001

Q 0.0041 o.oO04

One of the components is due to H2 (faster than Ho), one is due to Ho. and the third component, which has a very small amplitude, is a correction for the effect of the higher temperature trap (HHT).The amplitudes of H2 and Ho are comparable while their time constants are well separated. The effect of the higher temperature trap HHT is minimized by suitably reducing the total sampling time. The Arrhenius plot will be presented later since it will be compared with that found by SDLTS. 3) Comparison Between SRFM and MEFM in Characterizing H,: In order to compare the fitting results obtained by MEFM (pulsing the gate), SRFM (pulsing the substrate), GDLTS (peak position), and SDLTS (peak position with the time constant evaluated by the usual formula [12]) and the new formula ((A7) in the Appendix), their Arrhenius plots are presented in one graph and are shown in Fig. 10. First of all, the results obtained from SDLTS (triangles) peak position using the usual formula for the time constant [12] is about one decade smaller than that of the fitting using SRFM. If the time constant is evaluated using the new formula which assumes a nonexponential decay (open circles) then the SDLTS Arrhenius plot moves closer (almost the same) to that of SRFM. The results from pulsing the gate and the substrate are slightly different. This may be due to the fact that one of them has some unknown systematic errors. If this is the case then it is expected that the results obtained by MEFM are less accurate than those obtained by SRFM since in the former it is assumed that the individual transients are exponentials and that the total transient is the sum of the individual components. This assumption is questionable since the different traps are located in different regions in GaAs FET’s [9] and hence strictly different fitting formulas are needed for each trap. The individual transients

477

SENGOUGA A N D JONES: TRANSIENT RESPONSE OF SUBSTRATE TRAPS TO THE SUBSTRATE VOLTAGE

.. -

50

' * - - ' o

Tern pe rat ure/K

1

2.3

2.1

1M) 150 200 250 300 350 400 450

T

2.5

2.6

2.1

2.8

rl/i 0-V

2.9

3.0

3.1

Fig. 10. The Arrhenius plot of time constants evaluated by MEFM following a pulse applied to the gate to characterize Ho by GDLTS (full circles), by SRFM following a pulse applied to the substrate (squares), from GDLTS peaks (stars), from SDLTS using the well-known formula for the time constant ((A3) in the Appendix) (triangles), and from SDLTS using the new formula for the time constant ((A7) in the Appendix) (empty circles). The solid lines are for the Cr-related traps reported in the literature.

may not be simple exponentials as shown for the present two traps and another trap labeled H3 [ 191 and they may need to be added in a more complex manner. The results are summarized and compared with the parameters reported in the literature for the Cr level in Table VI. It can be said that Ho is the Cr level since the substrate used for the present device is doped with Cr. It is also well known that Cr may outdiffuse from the substrate [ 2 2 ] . Therefore, our conclusion that Ho is an interface trap is not surprising. We also believe that the parameters evaluated by SRFM are more accurate than the others because of the improvement in the characterization technique and accurate modeling. Now we discuss the emptying and filling rates for the two traps H I and Ho. The emptying and filling rates for H I are symmetrical as shown in Fig. 4 and comparing Figs. 1 and 1 1 . It was shown that H I is located in the SI substrate and in this material the position of the Fermi energy level at a certain temperature is imposed by the dominant trap level at that temperature which in this case is H I . Therefore, the position of the Fermi level is very close to that of H I causing the capture rate to be comparable to the emission rate as was discussed in the case of another trap labeled H3 [ 191. It can be seen that when a filling pulse is applied to the substrate, RSDLTS, as in Fig. 1 1, Ho is not observed with the normal exponential time constants whereas H , is almost the same as seen in Fig. l . The trap Ho does not have symmetrical filling and emptying rates (Fig. 1 1 ) . This is probably because Ho is not the only active trap at the characterization temperature. Hence the position of the Fermi level in the substrate is imposed by the combination of Ho with the other active traps ( H I and EL2). The activation energies for the observed traps are: EV + 0.71 eV for HI, Ec - 0.75 eV for EL2, and EV 1.03 eV for Ho. At the temperature where Ho is observed by DLTS, H I and EL2 are already fully ionized since they have faster emission rates than Ho (smaller activation

+

Fig. 1 1 . The typical RSDLTS spectrum for a device from the group F2 137 showing the symmetrical emptying and filling rates of H , as asymmetrical emptying and filling rates of Ho. The rate windows are the same as in Fig. 1 with which this curve should be compared. TABLE VI ~~

A E (eV)

0.96 I .03 0.96 0.94

U

(cm')

1.12 X IO-'' 1.07 X IO-'' 1.6 X IO-'' 2.7 X

Reference

Method

present work present work [25] 1171

Gate DLTS (MEFM) Substrate DLTS (SRFM) Gate DLTS DLTS (bulk and p-n junction)

energies). At this temperature, therefore, it is expected that the Fermi level will be well below the energy level of Ho and hence its filling rate is expected to be much faster than its emptying rate according to the detailed balance principle.

IV. CONCLUSIONS The time dependence of the device conductance due to emission from H I and Ho following an electric pulse applied to the substrate was accurately modeled. The accurate modeling showed that electrical means can be used to study traps in SI GaAs using a fitting method which takes into account the possible series resistance effect and the long filling time required. It was also shown that the conventional DLTS analysis technique can introduce large systematic errors in evaluating deep-level parameters. This is because in the conventional DLTS method it is assumed that the transient is a simple exponential decay. The errors introduced by the use of normal DLTS are eliminated using SRFM. Also the normal DLTS can still be used if the time constant is evaluated using the newly developed formula. It was also shown that the basic symmetry in emptying and filling rates for HI is due to the fact that the Fermi level position in the substrate, where the trap is located, is pinned near the trap level. The trap Ho does not have symmetrical and emptying rates since the Fermi level position in the substrate, where the trap is located, is determined by the combination of other traps in addition to Ho. A detailed study of the properties of H I and Ho using several additional techniques such as excess noise and gM dispersion has been made at Lancaster so that their results can be compared and will be presented elsewhere [ 13.

IEEE TRANSACTIONS ON

17x

APPENDIX ERRORSDUE TO NONEXPONENTIAL TRANSIENTS In the conventional DLTS, the transient decay in the capacitance or the conductance is assumed to have an exponential form, thus AC(t) oc exp

(-:).

S(T)

= W 2 )

- WI)

(-:)

- n2t:

where B is a constant. In conventional DLTS, (A2) should give a peak at 7 =

three possibilities to do this. One is to keep the ratio t 2 / t l constant while varying both t l and t 2 . The other two are to keep one of them constant and to change the other or vice versa. The simplest case is to keep the ratio constant because of obvious reasons [12]. Therefore, the simplest form of (A5) is t: exp

In this case the rate window DLTS signal is

t2 (t2 - t l ) / log -.

(A31

tl

Equation (A3) can be obtained by setting the derivative of (A2) with respect to 7 equal to zero. In the case of real GaAs FET’s, hole-like traps are not located in the bulk of the conducting channel. They are either surface- or interface-related traps [9]. Therefore, it is expected that the capacitance and conductances transient have nonexponential decay forms (see (8), (9), and [20]). For H I , for example, it was shown that the decay in the device conductance transient can be described by an equation of the form A. - A dl - exp ( - t / T ) . Therefore, the DLTS rate window signal is given by

S ( T ) = S(t2) - S(t1)

ELECTRON DEVICES, VOL. 40, NO. 3 , MARCH 1993

- t:

exp

exp

(-+)

(-?)+

n2t: exp

tl + 2ntl ( =0 7)

where n = r 2 / t l .In our case, for example, we have used n = 10. If we let x = exp ( - t l / 7 ) and since tl # 0 and x < 1 then the previous equation can be modified by using series expansion neglecting higher order terms to obtain a simplified equation of which the solution which is physically acceptable is

This value of T is approximately 5 times the usual one given by (A3). Therefore, it is expected that large errors would be introduced using the usual formula of the time constant.

ACKNOWLEDGMENT The authors would like to thank Plessey 3-5 for the specimens and discussions. The work benefitted from the collaboration of the other members of the group: M. A. Abdala and G. Jin.

REFERENCES The relation between 7 and the rate window ( t 2 , t l ) will be completely different from that given by (A3). Therefore, it has to be accurately evaluated. For this purpose by differentiating (A4) with respect to 7 and setting the result equal to zero and after some rearrangements we obtain

r: exp

(-:)

- ti

-

exp

t: exp

M. A. Abdala and B . K. Jones, Solid-Stare Electron., vol. 35, pp. 1713-1719, 1992. J. Barrera, in Proc. 5th Bienn. Cornel1 Electrical Eng. Conf., 1975, pp. 135-144. A. Broniatowski, A. Blosse, P. C. Srivastava, and J . C. Bourgoin, J. Appl. Phys., vol. 54, pp. 2907-2910, 1983. R . D. Fairman, F. J . Morin, and J . R. Oliver, Inst. Phys. Con$ Ser. NO. 45, pp. 134-143, 1979. N . Fourches, Appl. Phys. Lett., vol. 58, pp. 364-366, 1991. H . Grononkin, M. S. Birrittella, W . C . Seelbach, and R . L. Vaitkus, IEEE Trans. Electron Devices, vol. ED-29, pp. 845-850, 1982. T. Itoh and H . Yanai, IEEE Trans. Elecrron Devices, vol. ED-27, pp. 1037-1045, 1980. G . Jin and B. K. Jones, Semicond. Sei. Technol.., vol. 3, pp. 10831093, 1988. -, Semicond. Sei. Technol., vol. 5 , pp. 395-403, 1990. -, in preparation, 1993. C. Kocot and C. A . Stolte, IEEE Trans. Microwave Theory Tech., vol. MTT-30, pp. 963-968, 1982. D. V . Lang, J. Appl. Phys., vol. 45, pp. 3023-3032, 1974. D. V. Lang and R. A. Logan, J . Elecrron. Mat., vol. 5 , pp. 10531066, 1975.

( 24 + t2-7)

(-$) + t : exp ( t + 2t20. 7) =

To evaluate an activation energy and a capture cross section several sets of rate windows are needed. There are

SENGOUGA AND JONES: TRANSIENT RESPONSE OF SUBSTRATE TRAPS T O THE SUBSTRATE VOLTAGE

-, J . Appl. Phys., vol. 47, pp. 1533-1537, 1976. D. C. Look, K. R. Evans, and C. E. Stutz, IEEE Trans. Electron Devices, vol. 38, pp. 1280-1284, 1991. S . Makrem-Ebeid and P. Mimondo, in IEEE GaAs IC Symp., 1983, pp. 142-144. A. Mitonneau, G. M. Martin, and A. Mircea, Electron. Letr., vol. 13, pp. 666-667, 1977. N. Sengouga, Ph.D. dissertation, Lancaster University, Lancaster, UK, 1991. N . Sengouga and B. K. Jones, “Backgating and substrate conduction in GaAs FET’s,” submitted for publication, 1992. -, “Time and temperature dependence of backgating.” submitted for publication, 1992. E. Simoen, P. Clauws, and J. Vennik, J. Phys. D , vol. 18, pp. 20412058, 1985. B. Tuck, G. A. Adegboyega, P. R. Jay, and M. J. Cardwell, Inst. Phys. Conf: Ser. No. 45, pp. 114-124, 1979. J. F. Wager and A . J. McCamant, IEEE Trans. Electron Devices, vol. ED-34, pp. 1001-1007, 1987. N. Yokoyama, A. Shibatomi, S . Ohkawa, M. Fukuta, and H. Ishikawa, Inst. Phys. Con$ Ser. No. 336, pp. 201-209, 1977. A. Zylberstejn, G. Bert, and G. Nuzillat, Inst. Phys. Con6 Ser. No. 45, pp. 315-325, 1979.

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Nouredine Sengouga was born in Batna, Algeria, in 1962. He received the first degree (D.E.S. = Diplome d’Enseignement Superieur) in physical electronics from Batna University, Algeria, in 1985 and the Ph.D. degree from Lancaster University, Lancaster, UK, in 1991. The topic of his Ph.D. research was: Characterization and Effects of Hole Traps in GaAs-FET’s. He is now an Assistant Lecturer in the “Centre Universitaire de Biskra,” Biskra, Algeria.

Brian K. Jones (M’91) received the B.Sc. and Ph.D. degrees from the University of Bristol, Bristol, UK. He then took positions at NRC, Ottawa, Ont., Canada, and UCLA, Los Angeles, CA, before his present position at Lancaster University, Lancaster, UK. His research has gradually changed from low temperature and the physics of metals to the present emphasis on electric noise, defect properties, and reliability in electronic devices.