Signal-Powered Low-Drop-Diode Equivalent Circuit for ... - IEEE Xplore

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 10, OCTOBER 2012

Signal-Powered Low-Drop-Diode Equivalent Circuit for Full-Wave Bridge Rectifier Laxmi Karthikeyan and Bharadwaj Amrutur, Member, IEEE

Abstract—Piezoelectric-device-based vibration energy harvesting requires a rectifier for conversion of input ac to usable dc form. Power loss due to diode drop in rectifier is a significant fraction of the already low levels of harvested power. The proposed circuit is a low-drop-diode equivalent, which mimics a diode using linear region-operated MOSFET. The proposed diode equivalent is powered directly from input signal and requires no additional power supply for its control. Power used by the control circuit is kept at a bare minimum to have an overall output power improvement. Diode equivalent was used to replace the four diodes in a fullwave bridge rectifier, which is the basic full-wave rectifier and is a part of the more advanced rectifiers like switch-only and bias-flip rectifiers. Simulation in 130-nm technology and experiment with discrete components show that a bridge rectifier with the proposed diode provides a 30–169% increase in output power extracted from piezoelectric device, as compared to a bridge rectifier with diodeconnected MOSFETs. The bridge rectifier with the proposed diode can extract 90% of the maximum available power from an ideal piezoelectric device-bridge rectifier circuit. Setting aside the constraint of power loss, simulations indicate that diode drop as low as 10 mV at 38 μA can be achieved. Index Terms—Full-wave bridge rectifiers (FBRs), low-dropdiode equivalent (LDDE), piezoelectric devices (PZDs), synchronous rectifiers, vibration energy harvesting.

I. INTRODUCTION MBIENT vibration energy can be harvested and converted to useful electrical energy. The electrical energy can be used for powering low-power electronic systems such as sensors, microelectromechanical systems devices, or implantable medical electronics. Vibration energy can be harvested using various types of transducers such as electromagnetic, electrostatic, or piezoelectric. Electromagnetic-device-based harvesters employ a coil to tap energy from a moving magnetic field produced by magnets, which move in the ambient vibration [1]. In electrostatic energy transducers, vibration leads to a relative parallel motion between an electret and nearby metallic surface [2]. This leads to induced counter charge on the metal, with the charge simply following the relative motion of the electrets. This produces an electric current. Piezoelectric harvesters work by stressing a piezoelectric material in accordance with the vibration and tapping the generated electric charge from the material.

A

Manuscript received July 7, 2011; revised July 7, 2011; accepted February 27, 2012. Date of current version May 31, 2012. Recommended for publication by Associate Editor E. Santi. The authors are with the Department of Electrical Communication Engineering, Indian Institute of Science, Bengaluru 560012, India (e-mail: [email protected]; [email protected]). Digital Object Identifier 10.1109/TPEL.2012.2190828

Electrical energy from any vibration energy harvester device is converted to a load-usable form by an interface circuit, which is connected between the device and its load. The interface circuit consists of a rectifier–filter section for conversion of input ac to dc. The diodes in the rectifier conduct with a voltage drop, leading to power loss. The power loss due to diode drop is a significant fraction of the overall harvested power (10–100 μW [3], [4]). It is, therefore, required for the diodes to conduct with minimum voltage drop. Hence, there is a need of a low-drop-diode equivalent (LDDE), which can be used to replace the rectifier diodes. In particular, the LDDE should be able to replace the four diodes in full-wave bridge rectifier (FBR), as FBR is the most common circuit reported in the energyharvesting literature, sometimes referred to as the standard [5]. The LDDE should meet the following requirements; 1) it should have a very low forward conduction drop; 2) it should block any reverse conduction; 3) it should be able to replace the four diodes in FBR; 4) it should not use an additional external power supply; 5) it should be powered directly from input signal and not from harvested power. This is to use the available input power instead of the extracted output power; 6) it should not demand additional off-chip components; 7) the control circuit should draw minimum power. We propose an LDDE, which meets all of the aforementioned requirements. The LDDE is based on mimicking a low-drop diode with a MOSFET operated in linear region. Such a MOSFET which is controlled such that it conducts in the deep triode region in one direction and goes into subthreshold region (OFF state) in the other direction is called a synchronous rectifier. Previous implementations have also used synchronous rectifiers. However, their control circuit does not meet all of the aforementioned conditions 1–7. CMOS control rectifiers in [6] and [7] and the synchronous full-wave rectifier in [8] need an external power supply for powering up the comparator. Le et al.[8] also suggest a passive full-wave rectifier. It, however, requires additional off-chip capacitors. It is also less power efficient owing to the continuous conduction of two diodes by drawing power from the output and also due to reverse conduction by a transistor in saturation region. It also does not show the implementation in FBR. In [9], a second piezoelectric patch is used to create two stable supply voltages to supply energy to a comparator. In [10], an additional input is required which is 180◦ out of phase with the input for full-wave rectification. The proposed LDDE can also be used in voltage multipliers [5], [11] and charge pump [12]. A voltage multiplier with output-powered active diodes is shown in [13]. In [14], a

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KARTHIKEYAN AND AMRUTUR: SIGNAL-POWERED LOW-DROP-DIODE EQUIVALENT CIRCUIT FOR FULL-WAVE BRIDGE RECTIFIER

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TABLE I P E X T ( m a x ) OF VARIOUS RECTIFIER ARCHITECTURES

Fig. 1.

Equivalent circuit of a PZD at resonance.

current-sensing approach is used for generating the gating signals of output-powered comparator of the MOSFET-based active rectifier. Being output powered, diodes in both [13] and [14] consume standby power. In [15], a MOSFET-based full-wave rectifier followed by a diode to block reverse current conduction is used. The diode is implemented as an active diode powered from the output. The circuit has greatly reduced the diode drop and improved the efficiency. However, the active diode consumes standby power. This issue has been taken care of, in [16] with an input-powered full-wave rectifier and active diode. In [5], the use of gate cross-coupled topologies of MOSFET-based FBR is indicated. This improves the power conversion efficiency. The ideas in [5] and [16] are specific to FBR implementation and are not of a stand-alone LDDE. The synchronous rectifier in [17] suggests a stand-alone LDDE. But it allows reverse conduction. Though the reverse current level can be made small, it cannot be neglected when used in low-power circuits like vibration energy harvesters. There is also a resistor– diode (diode-connected MOSFET) path which is continuously conducting leading to power loss. Work in [17] and [18] has not been suggested for low power (10–100 μW) application. In this paper, we have proved the efficacy of the proposed LDDE in a piezoelectric device (PZD)-based vibration energyharvesting system. The electrical equivalent of a PZD [3] when it is vibrated at its resonance frequency is shown in Fig. 1. Ip is a sinusoidal current source with amplitude equal to Ip p e a k . Ip p e a k depends on the amplitude of vibration and the frequency fp of the current source is equal to the frequency of vibration. Resonant frequency of the PZD is assumed to match with fp . From Fig. 1, it is seen that the maximum available power from the PZD with conjugate matching of load is given by PPZD ( m a x ) =

Ip2p e a k · Rp 8

.

(1)

When the rectifier–filter section is introduced at the output of PZD, it sets a further limit on the maximum available power to the load. Let this limit on the maximum available or extractable power be represented by PEXT ( m a x ) . Then, PEXT ( m a x ) ≤ PPZD ( m a x ) . The proposed LDDE can replace the diodes in various architectures of rectifiers used for PZD-based harvesting. These architectures include conventional FBR, switch-only rectifier [3], [19], bias-flip rectifier [3], series synchronized switching harvesting with inductor (SSHI) [20], [21], synchronous charge extraction circuit [20], [22], voltage doubler [3], resonant rectifier [23], and pulsed-resonant micropower converter [24]. Makihara et al. [25] suggest SSHI with two rectification diodes instead of four. Series SSHI with magnetic rectifier [26] uses a transformer to reduce the effective diode drop by a factor equal to

the transformer ratio. The PEXT ( m a x ) is dependent on the architecture of rectifier. The SSHI and resonant architectures provide a high PEXT ( m a x ) , as compared to the conventional FBR. Table I gives the PEXT ( m a x ) of different architectures. From Table I, it is seen that for all rectifier architectures, PEXT ( m a x ) increases as the rectifier diode drop decreases. The remainder of this paper is organized as follows. Section II covers the working principle and power considerations of the proposed LDDE. Section III gives the design considerations and the simulation results in 130-nm technology. Section IV describes the detail of an experiment with the proposed LDDE, implemented with discrete components. Finally, Section V concludes this paper. II. WORKING PRINCIPLE OF THE PROPOSED LDDE A MOSFET operated in linear region (deep triode region) exhibits a very low value of dc resistance. It can conduct with lesser voltage drop for the same current, as compared to a diode or a diode-connected MOSFET (DCMOS). This property of MOSFET is exploited to use it to mimic a low-drop diode. It may also be noted that a DCMOS cannot be used as a low-drop diode, because of a minimum drop across it which is equal to the threshold voltage of MOSFET. In the proposed LDDE, MOSFET is controlled such that it conducts only in one direction (call forward direction) and in linear region in the forward direction. The control circuit is designed such that it draws power directly from the input signal, so that no external supply is required. A circuit diagram of the proposed LDDE is shown in Fig. 2. Source of PMOS (M1 ) acts as the anode and drain of M1 acts as the cathode of LDDE. The emitter–base junction of p-n-p transistor (T1 ) is across (in parallel with) the source–drain of M1 . Substrate of M1 is kept connected to drain to block reverse conduction. To illustrate the LDDE operation, the following step-by-step description is given: 1) When LDDE sees a voltage in the forward direction (positive signal voltage), the emitter–base junction of T1 is forward biased and T1 begins to conduct. 2) When T1 conducts, it provides the base drive current to n-p-n BJT (T2 ) and T2 enters into conduction. 3) The gate–source capacitance Cgs of M1 gets connected across the PZD through T2 and Cgs starts getting charged in the negative direction.

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Fig. 3. Fig. 2.

NMOS-based implementation of LDDE.

Circuit diagram of the proposed LDDE.

4) When the source–gate voltage Vsg of M1 exceeds the threshold voltage of M1 , M1 starts conducting. 5) Cgs of M1 continues to get charged and Vsg of M1 keeps increasing. As Vsg keeps increasing, M1 enters from the saturation region into linear region. 6) When M1 enters the linear region of conduction, the source–drain voltage of M1 (Vsd ) reduces to a very low value. 7) Since the voltage across emitter–base junction of T1 reduces, T1 turns OFF. 8) When T1 turns OFF, T2 turns OFF. 9) Cgs of M1 stops getting charged. However, Cgs has no path to discharge and Vsg is maintained. This enables M1 to continue conducting in the linear region. After M1 starts conducting in the linear region, the drop across the parallel combination of M1 source–drain and T1 emitter–base junction is dictated by the linear region characteristic of M1 . The drop across anode and cathode of the LDDE thus becomes equal to that across a MOSFET in linear region. 10) When signal reverses, signal R gets activated (generation of signal R is discussed shortly). Signal R is a one-diodedrop positive signal w.r.t cathode of LDDE (or anode of LDDE, cathode and anode being at almost the same potential). 11) Signal R turns ON the NMOS (M2 ), which discharges Cdg of M1 and turns M1 OFF to prevent reverse conduction. A. Current Reversal Sense Circuit The reversal of current is sensed using the current reversal sense circuit (CRSC), as shown in Fig. 4, and fed as signal R. Diodes D1 , D2 , D3 , D4 and capacitor Cs form the CRSC. When Ip makes a zero-crossing from negative to positive, current flows into Cs through the D2 -Cs -D4 path. This keeps diodes D2 and D4 forward biased during the transition of Ip from negative to positive. The voltage at Pin 2 with respect to Pin 1 is negative and the voltage at Pin 3 w.r.t. Pin 4 is positive. Similarly, during the zero-crossing of Ip from positive to negative, the voltage at Pin 2 w.r.t. Pin 1 is positive and the voltage at Pin 3 w.r.t. Pin 4 is negative. Ip transition direction is, thus, indicated by either of voltage at Pin 2 w.r.t. Pin 1 or voltage at Pin 3 w.r.t. Pin 4.

At the resonant frequency fp , the voltage across CRSC diode around zero-crossing is given by VD ( C R S C ) =

ip · RD 1+

Cp Cs

D + j (2π f2R −1 p Cp )

(2)

where RD is the resistance of conducting diode, ip is the instantaneous value of Ip , and Rp is ignored. Cp D From (2), it is seen that for (2π f2R −1 C , the zerop ·C p ) s crossing of Ip is detected (in the form of VD ( C R S C ) ) with minimum lag. It may also be noted that two resistors can be used instead of the four diodes. Diodes are, however, used to limit the gate voltage of M2 (see Fig. 2) w.r.t. its source/drain voltage. B. FBR With the Proposed LDDE (See Fig. 5) DM1 and DM2 are PMOS-based implementations of diode. DM3 and DM4 are NMOS-based LDDE. NMOS-based LDDE, as shown in Fig. 3, is the complementary counterpart of PMOSbased LDDE. Co is the filter capacitor and RL is the load resistor.

C. Power Considerations The control circuit in LDDE does not need an external power supply. Power is drawn directly from PZD. The additional power consumption as compared to conventional DCMOS is by T1 and the gate capacitance of M2 . T1 , however, conducts only for a short duration at the beginning of the conducting half cycle. Also, the current flowing through T1 is very low as it is the base current of T2 . The gate capacitance of M2 can be kept low by sizing M2 to a low dimension, without drastically affecting the time taken to discharge Cdg of M1 . So the additional power consumption is very less. The CRSC also takes power directly from PZD and does not need an additional power supply. Power drawn by CRSC is negligible as the capacitance of Cs is very 1 ) as compared to Cp . small (about 1000 As with any synchronous rectifier, the charging and discharging of gate capacitance (C) of M1 consumes power. The higher the voltage V to which it is charged, the higher is the switching loss (CV 2 fp ). However, the equivalent diode drop decreases with increase in V.


Fig. 4.

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CRSC. Fig. 6.

Variation of extracted power and control power with diode drop.

A. PZD Equivalent Circuit Cp and Rp are assigned values of 26 nF and 700 kΩ, respectively. The frequency fp of the sinusoidal current source Ip was set at 85 Hz. All values are based on the commercial PZD, Mide Volture V21BL. B. Circuit Design Considerations

Fig. 5.

FBR and filter for PZD using the proposed LDDE.

D. Usability of LDDE in Other Rectifier Circuits The LDDE has two additional pins, “C” and “R” apart from the anode and cathode of an ordinary diode. When using a PMOS-based LDDE, the anode “P” and cathode “N” are connected as in the case of a normal diode. Connections of “C” and “R” are described as follows: 1) “C” is connected to a point in the circuit which, when the LDDE is conducting, would be at least one threshold voltage below the point to which anode “P” of LDDE is connected; 2) “R” is generated by connecting the CRSC across “P” and “C” and tapping out Pin 2 of CRSC as “R.” The connection of NMOS-based LDDE can be mapped on a complementary basis.

III. VERIFICATION BY SIMULATION The circuit in Fig. 5 was verified by the simulation. It was simulated using Virtuoso Spectre Circuit Simulator with United Microelectronics (UMC) 130-nm library models. Triple-well technology (TWT) models were used due to the requirement of connecting the substrate of NMOS transistors to the respective source/drain. MOSFETs with a maximum voltage rating of 3.3 V were used, which was the highest available in 130-nm UMC process. The BJTs used were TWT vertical BJTs. Capacitor Cs of CRSC was a metal–insulator–metal capacitor. Co , the filter capacitor in the microfarad range, was taken as an off-chip component. D1 –D4 are process p-n diodes.

With reference to Fig. 2, M1 was sized according to the specified maximum current (peak value of Ip ). M2 was sized to the minimum dimension to reduce power loss. T2 was a set of parallel BJTs. The number of BJTs in the parallel connection was set to an optimum value. The higher the number of BJTs, the faster is the charging of Cgs of M1 and higher is the Vsg of M1 . This leads to two opposing effects on the output power. 1) M1 gets pulled deeper into the triode region, which reduces the LDDE forward conduction drop. This tends to increase the output power Po , by increasing the extracted power Pextd . 2) For higher Vsg , the power spent in charging and discharging of M1 increases. This tends to decrease Po by increasing the control power Pc Po = Pextd − Pc .

(3)

Thus, there is the need of an optimum number of parallel BJTs, so that Po is the maximum. Corresponding to the optimum number of BJTs, there exists an optimum diode drop. Fig. 6 shows the increase in Pextd and control power Pc with the decrease in diode drop. Fig. 7 shows that Po maximizes at a diode drop of 56 mV. T1 was also a set of parallel BJTs. The number of T1 s was decided by the number of T2 s. C. Simulation Results The circuit was simulated at an amplitude of Ip (Ip p e a k ) = 60 μA. The optimum value of load resistance RL , corresponding to the maximum output power, was determined by varying RL and plotting output power, Po versus RL (see Fig. 8). Optimum value RL o p t was determined to be 107 kΩ. All simulation results were taken at RL o p t , unless otherwise stated.

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Fig. 7.


Variation of output power with diode drop.

Fig. 9. Start-up waveforms of LDDE-based FBR at Ip p e a k = 25 μA and fp = 85 Hz.

Fig. 8.

Variation of output power of LDDE-based FBR with load resistance.

It may be noted that Po is calculated by measuring Vo as Po =

Vo2 . RL

PEXT−FBR ( R L ) = (4)

The circuit was simulated at various values of Ip p e a k . The LDDE forward conduction drop VD , LDDE current, gate control voltage of LDDE, and output voltage Vo were plotted (see Figs. 9 and 10). The output power was calculated in each case. From Table I, PEXT ( m a x ) of FBR, in the best case of VD = 0, is given by PEXT−FBR ( m a x ) = Cp · Vp2 · fp .

(5)

The efficiency of output power extraction was calculated w.r.t. this maximum possible available power from PZD-FBR (PEXT−FBR ( m a x ) ). The efficiency of output power extraction is calculated by η=

Po PEXT−FBR ( m a x )

.

resistance RL is given by

(6)

Table II gives the η at various values of Ip p e a k . The theoretical output power from a PZD-FBR at VD = 0 and at any load

2

Ip2p e a k (1 − cos2 θ) ((2π)2 · fp · Cp )

(7)

θ) where RL = (4·f p (1−cos ·C p (1+cos θ ) 2 ) and θ is the nonconduction angle in Ip half cycle. By simulation, power depreciation at the output from the theoretically predicted values of output power for an ideal PZDFBR was determined as a function of Ip p e a k for different values of RL . Rp was ignored in the simulation. Power deficit has been plotted in Fig. 11(c). The characteristic of power deficit is explained using the output voltage Vo and diode drop curves [see Fig. 11(a) and (b)]. Vo is a direct indicator of the Vgs of M1 (see Fig. 2), as shown in Fig. 10, and hence of the CV 2 fp switching losses in the gate capacitance of M1 . Diode drop is a pointer to the conduction loss (VD · Ids ), where Ids is the source current of M1 which can be approximated to Ip during diode conduction. For low values of Vo , M1 is not in the deep triode region, as shown by the diode drop curves. For RL = 80 kΩ, deep triode region is entered at Ip p e a k ≈ 40 μA. For RL = 113 kΩ and 160 kΩ, deep triode region is already entered at Ip p e a k of 30 μA.


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Fig. 10. Steady-state waveforms of LDDE-based FBR at Ip p e a k = 25μA and fp = 85Hz.

TABLE II P o AND η OF LDDE-BASED FBR AT VARIOUS VALUES OF Ip p e a k

Fig. 11. Performance of LDDE-based FBR as a function of Ip p e a k for various R L . (a) Output voltage. (b) Diode drop. (c) Power deficit.

When not in the deep triode region, conduction loss is the major loss. As RL increases for a fixed Ip p e a k , Vo increases, Vgs increases, VD decreases, and, hence, conduction loss decreases with the increase in RL . The decrease in conduction loss is also due to the lesser conduction period as RL increases. Also, when not in the deep triode region, as Ip p e a k increases at a fixed RL , Vo increases, Vgs increases, VD decreases at a faster rate than Ip p e a k increases, and thus conduction loss decreases. When M1 enters into the deep triode region, switching loss dominates. For a fixed RL , as Ip p e a k increases, Vo increases, Vgs increases, and switching loss increases. The conduction loss

also increases, as in the triode region, Vds increases with Ids (or Ip p e a k ). For a fixed Ip p e a k , as RL increases, Vgs increases leading to higher switching loss. The variation in Vds (or VD ) with RL is insignificant in the deep triode region. For comparison with the standard DCMOS, the FBR-filter section of PZD was wired with DCMOS and simulated. The DCMOSs used were of the same type and dimension, as M1 (see Fig. 2) of LDDE, to enable the best comparison. RL o p t of DCMOS-based FBR was found to be 111 kΩ. Figs. 12 and 13 show that the LDDE scores over DCMOS both in terms of lower VD and higher Po . Po is higher by up to 169% for low values of Ip p e a k and by up to 30% at higher values of Ip p e a k . This trend can be understood from PEXT ( m a x ) of FBR, as given in Table I.

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TABLE III COMPARISON OF THE PROPOSED LDDE-BASED CIRCUIT WITH PREVIOUS IMPLEMENTATIONS

Fig. 12.

Comparison of diode drop of LDDE with that of DCMOS.

E. Comparison With Previous Implementations

Fig. 13. Comparison of output power of LDDE-based FBR with that of DCMOS-based FBR.

D. General Remarks In Fig. 12, it is noted that the LDDE forward conduction drop decreases with the increase in Ip p e a k for low values of Ip p e a k and starts increasing with Ip p e a k for higher values of Ip p e a k . Referring to Fig. 2, it is observed that for low values of Vp , transistor T1 is not sufficiently conducting to turn ON the transistor T2 fully. This leads to lesser charging of Cgs of M1 . So M1 cannot be pulled into the deep triode region. As a result, Vsd of M1 will be higher than when in the deep triode region. As Vp increases, T1 conducts better leading to a better T2 conduction and better charging of Cgs . This leads to M1 being pulled more into the triode region, reducing the Vsd of M1 . But beyond the value of Vp at which M1 is pulled well into the triode region, Vsd increases with Ip p e a k or Vp as the source current of M1 increases with Ip p e a k . The circuit was designed with an aim to maximize the output power from FBR-filter section. The diode drop has been optimized to a value which gives the maximum output power. The diode drop can be reduced to even lower values with the same circuit by increasing the number of parallel BJTs for T2 (see Fig. 2). However, it leads to higher power consumption with respect to charging and discharging of M1 (see Fig. 2), as explained in Section III-B. Setting aside the constraint of power loss, diode drop as low as 10 mV at 38 μA can be achieved, as indicated by Figs. 6 and 7.

Table III gives the comparison of the proposed LDDE-based circuit with previous implementations. It may be noted that FBR implementation theoretically provides lesser power efficiency than voltage doubler for the same type of diode equivalent. This is because of the following: 1) for a diode drop, VD , and under the same input conditions, the PEXT ( m a x ) of FBR is lesser than that of voltage doubler, as shown in Table I; 2) the total control power of the diode equivalents is more for FBR as there are four diodes, as against two in voltage doubler. However, FBR implementation has been taken up in this study, because it is a generic rectifier, which is used in the more advanced rectifiers such as bias-flip rectifier and switchonly rectifier. Furthermore, the proposed LDDE can be used in voltage doubler also. Lim et al. [17] provide a diode drop of 10 mV. The proposed work can also provide a diode drop of 10 mV, as indicated by Figs. 6 and 7.

IV. EXPERIMENTAL VERIFICATION The FBR-filter section of the interface circuit for PZD-based vibration energy harvesting was rigged up using discrete components. Specified working of the proposed LDDE was verified by wiring it up using discrete components and using it in place of the four diodes in FBR. To enable comparison with the conventional DCMOS, the FBR-filter was configured, both using the proposed LDDE and conventional DCMOS.


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TABLE IV LIST OF COMPONENTS USED IN THE EXPERIMENT

Fig. 15. Variation of the proposed LDDE-based FBR output power with load resistance (frequency of vibration = 85 Hz; acceleration = 0.5g).

Fig. 14.

Experimental setup.

A. PZD Detail The PZD used was Mide Volture V21BL. It has two piezoelectric strips on the same substrate, but with independent electrical wiring. Each strip has a Cp of 26 nF.

Fig. 16. Output of LDDE-based FBR at 0.8g, 85 Hz vibration of PZD (reproduced from digital oscilloscope-recorded data points). (a) PZD output. (b) FBR-filter output.

B. FBR Circuit Details The LDDE-based FBR was configured using discrete components, as shown in Table IV. The DCMOS-based FBR was configured using the same type of MOSFET as used for LDDEbased FBR to enable the best comparison. C. Experimental Setup The PZD was mounted along the datasheet-specified clamp line in a cantilevered configuration on the LDS Dactron shaker, as shown in Fig. 14. The two electrical wires corresponding to one of the piezostrips were taken out and connected to the input of FBR. The wires taken out were arrested properly after giving them enough stress relief. The voltage across different points in the circuit was measured using a digital storage oscilloscope. The LDS Dactron Shaker gives calibrated sinusoidal vibration in the vertical direction at user-set frequencies and amplitudes (given in terms of acceleration g). D. Measurement Results 1) Determination of resonance frequency of PZD: The PZD was vibrated at various frequencies from 50 to 500 Hz at a fixed amplitude of 1g. The amplitude of sinusoidal output from PZD peaked at 85 Hz. Resonance frequency = 85 Hz.

Fig. 17. Output power of LDDE-based FBR at different frequencies and amplitudes of vibration of PZD.

2) Determination of optimum load for the PZD-rectifier circuit: The PZD was vibrated at 85 Hz, 0.5 g, and the output voltage Vo from the FBR filter was noted at various values of load resistance RL . Output power Po in each case was calculated from (4). Output power peaked at RL =100 kΩ (see Fig. 15). Optimum load resistance = 100 kΩ. RL was kept fixed at its optimum value during the rest of the experiment. 3) Characterization of LDDE-based FBR: The PZD was vibrated at various frequencies from 50 to 500 Hz and amplitudes from 0.5g to 1g. The output voltage Vo of

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Fig. 18. Comparison of forward conduction drop of LDDE with DCMOS (Vibration Frequency = 85 Hz).


LDDE-based FBR was measured (see Fig. 16) and recorded in each case. The output power was calculated from (4). A 3-D plot of output power was made based on these data (see Fig. 17). 4) Comparison of performance of LDDE with that of DCMOS: The PZD was vibrated at various frequencies from 81 to 89 Hz and amplitudes from 0.3g to 1g. Rectified voltage at the optimally loaded output of FBR and the diode drop were measured in both the configurations, viz., LDDE-based and conventional DCMOS-based. Output power was calculated using (4). Figs. 18–20 show that the proposed method has a strict advantage over conventional method in terms of lower diode drop and higher output power, under same input conditions. In general, the LDDE-based FBR provided a 65–104% increase in power as compared to the DCMOS-based FBR. V. CONCLUSION A linear region-operated-MOSFET-based LDDE has been proposed. It can be directly powered from input signal and requires no additional power supply. The proposed diode equivalents have been used to replace the four diodes of FBR in PZD interface circuit. The efficacy of the proposed diode in decreasing the diode drop and increasing the output power from a PZDbridge rectifier circuit has been demonstrated through simulation in 130-nm technology and experiment with discrete components. It provides a 30–169% increase in output power as compared to a bridge rectifier with conventional diode-connected MOSFETs. The simulation in 130-nm technology also shows that it can extract 90% of the maximum available power from an ideal PZD-bridge rectifier circuit. Setting aside the constraint of power loss, simulations indicate that a diode drop as low as 10 mV at 38 μA can be achieved.

Fig. 19. Comparison of output power from LDDE-based FBR with that from DCMOS-based FBR (Vibration Frequency = 85 Hz).

ACKNOWLEDGMENT The authors would like to thank the Department of Information Technology, Ministry of Communications and Information Technology, Government of India, for the funding support provided toward the installation of simulation software. The cooperation received from ISRO is gratefully acknowledged. They are also grateful to Prof. G. K. Anantha Suresh and Prof. T. V. Prabhakar for facilitating the successful completion of the experiment. REFERENCES

Fig. 20. Comparison of output power from LDDE-based FBR with that from DCMOS-based FBR (Vibration acceleration = 1g).

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Laxmi Karthikeyan received the B.Tech degree in electronics and communication from the Cochin University of Science and Technology (CUSAT), India, in 2005, and the M.E degree in microelectronic systems from the Indian Institute of Science, Bangalore, India, in 2011. She worked as a System Engineer in Siemens Information Systems Ltd, Bangalore, India, for a short period in 2005. From 2006, she is working as a Scientist/Engineer in the Indian Space Research Organisation (ISRO). Her research interests are in Analog Electronics and Power Electronics.

Bharadwaj Amrutur (M’08) received the B.Tech. degree in computer science and engineering from the Indian Institute of Technology, Bombay, India, in 1990 and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Palo Alto, CA, in 1994 and 1999, respectively. He has worked at Bell Labs, Agilent Labs and Greenfield Networks. He is currently an Associate Professor in the Department of Electrical Communication Engineering, Indian Institute of Science, Bangalore, India, where he is working in the areas of VLSI Circuits and Systems.