features of USB 2.0 which are currently posing in SOC validation. This could be a systematic cause many issues because of the easiness to sitting inside FPGA.
2014 15th International Microprocessor Test and Verification Workshop
PHY A FPGA Bassed Ecosystem for USBP Validation Maneesh Kumar Paandey1, Shwetank Shekhar2, Amit Sinha3 Arun Mishrra4 Freeescale Semiconductor India Pvt. Ltd., Noida, Uttar Pradesh 1, 2, 3, 4 (maneesh.pandeey; shwetank.shekhar; B10813, B13471)@freescale.com
before going into the product. Oncee the USB specification [1] is validated then the system level testing can be performed without USBPHY failure.
Abstract— SOCs are getting complex daay by day which makes IP design reuse a key approach. To prove functional performance of the IP in SOC, stimulus iss required which activates the particular feature of the logic and ooutput is matched with the golden values. Real time experience sh hows that it is not feasible to test all the features of the IP in SOC, specially negative scenarios such as timeout while enumerating tthe device. In this paper we propose a novel Validation Frameworrk which validates USBPHY-IP as slave controlled by prototype model implemented in FPGA. Modifications are made in IP as soon as bugs are found P finally occupies and after successful validation (zero bugs), IP space into SOC. This approach is capable off checking all the features of USB 2.0 which are currently posing major challenges in SOC validation. This could be a systematic approach to root cause many issues because of the easiness too play with logic sitting inside FPGA. This paper discusses the ch hallenges for USB PHY IP validation and addresses the issues usin ng this innovative framework. Some of the results are presented in n the form of case studies for 45nm silicon.
This paper is organized in five sections. Section II explains s one validation framework. the reasons for adopting standalo on of proposed Validation Section III has complete descriptio Framework which can reduce the validation cycle that can further help in reduction of time to market. Section IV has couple of case studies on USB PH HY IP validation using this setup at C45SOI silicon. Section V is more about drawing conclusions considering various imp portant points. II.
In Systems level Validation [10] (Figure 1) USBPHY-IP directly goes into SOC. This makes SOC validation troublesome because of the followin ng reasons. •
PGA, SOC, IP Keywords— USB PHY, ULPI, Validation, FP
I.
E VALIDATION ECOSYSTEM REASONS FOR STANDALONE
INTRODUCTION
Functionalities of conttroller are fixed and there exist no possibility to test all scenarios specially the negative ones. So, there is limited scope for IP t validation and debug.
Designers all over the world are facing inccreasing pressure to design smaller products in lesser time annd at lower cost. Integrating the physical layer (PHY) analoog circuitry in a cutting edge technology such as USB is a comp mplex task that has become a technical challenge requiring more man-hour, more investment, and more silicon re-spins. To meeet time to market while keeping the cost low, physical layer is provided in a separate chip. This external PHY with UL LPI (UTMI Low Power Interface [3][4]) interface is testeed rigorously in validation . If the Compliance testing of ULPI-PHY silicon has been done properly then there should not be anyy need to go for further testing/debugging. The compliance teesting [7][8][9] is generally done at system level. Any failure seen in compliance tests is difficult to root cause due to limited ddebug capabilities of system level setup. To avoid this limiitation, a Novel USBPHY-IP Validation Framework has beeen introduced. A USBPHY-IP Validation Framework is a setupp which contains USB PHY and USB controller on two differeent boards which are connected through the ULPI interface [5]. Functionalities of USBPHY specification are validatedd in standalone framework so that bugs of design are rectifiedd in initial stages 1550-4093/15 $31.00 © 2015 IEEE DOI 10.1109/MTV.2014.12
Figure 1: system Levell USBPHY Validation Setup
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•
III.
If there is any issue, first it needs to be identified and sorted out as whether the issue belongs to controller or PHY, but segregatting the issue is quite a tedious task as many m more players (e.g. System bus, Core, clock domainns etc) come into picture.
NOVEL STANDALONE USBPHY VALIDATION ECOSYSTEM
In this setup USB PHY EVB is interfaceed with a FPGA board through the ULPI Interface [6] as shoown in figure 4. FGPA board contains basic USB 2.0 link controller codes which have capabilities of register read/wriite (Figure 2) & transmitting data (Figure 3). FPGA board is controlled by LabView software running at PC through thhe RS232 port as shown in figure 4. [14] ULPI signals are monitored at Logic Analyzer (LA). Oscilloscope with USB software [12] is useed to analyze the USBPHY HS, FS and LS mode signals. Usingg this setup all the parameters mentioned in the ULPI specificatiion can be tested [6].
Figure 3: LabView GUI for Data Transmit T USBPHY Validation
USB-PHY validation is done according to well define validation plan which contains all parameters given in the ULPI specification [5].
Figure 4: Standalone USBPH HY Validation Setup
With this setup some of the im mportant ULPI specification test results are shown below.
Figure 2: LabView GUI for Register Read/Write US SBPHY Validation
A. HS Data Transmission: HS data [DD, 0D, 6F, 64, 10, 7A] is transmitted through Lab View software on the link thaat is captured at LA (Logic Analyzer) as shown in figure 5. In n this figure, it can be seen that ‘Dir’ signal is low (indicating data is transmitted by the Link) and NXT is high when data d comes at data lines (indicating PHY asserts NXT signal while receiving data from the link).
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Figure 5: HS data transmission Figure 7: HS Receive data at 180mV (Data line and DC Squelch)
B. Register Read: PHY is configured in Full Speed (FS) mode through LabView software, the value in Function Control register is read through LabView and is observed at LA (figure 6). The value of this register comes 0x45 in FS mode.
D. HS Eye Diagram: PHY is configured in HS Host/Device mode. Test-Packet is generated using LabView (shown in Figure 2). High Speed Eye is plotted at DP/DM using scope as shown in figure 8 [11]. These tests were done using FPGA based customized link controller, lab view application and USBPHY test chip. Using same approach all other specification of USBPHY [2] can also be validated.
Figure 8: HS Eye Diagram Report is generation using Novel Setup Figure 6: ULPI Register Read
C. HS Receive data at Squelch line: When Data is received by PHY, the squelch line goes low as shown in figure 7.
IV.
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CASE STUDIES OF USBPHY-IP VALIDATION USING NOVEL ECOSYSTEM
adjusted setup time below 5ns on which USB-PHY was working properly.
Some of the USB2.0 specification provided by USB-IF are complex and difficult to validate at system level which are presented below as case studies using above setup: A. Transmit Error: In case when link forces data 0xFF for more than one clock cycle on the bus, PHY will automatically generate the FS transmit error by sending a minimum of 8 consecutive 1's on the USB bus. Problem: Observing this transmit error on USB bus was very tedious task with legacy setup in validation as link can’t send this type of data for more than one clock cycle in traditional setup. But at our validation setup, transmit error can be observed by writing code in FPGA in such a way that this scenario can be created. B. PHY Safeguard Test: In PHY safeguard test, ULPI data and STP lines need to be floating. Attaining this condition is quite difficult with the traditional validation method. This can be easily done when the PHY and Controller are on two different boards. Using the FPGA, the ULPI data and STP lines can be made floating. Once data and STP lines are floating, PHY safeguard test can be performed.
Figure 9: setup for setup time testing
D. HS Transmit Data Signal: In our experiment, there was a problem in taking HS eye diagram because the HS signals on DP and DM were nearly half of the actual amplitudes as shown in figure 10.
C. Setup and Hold time measurement with respect to PHY clock.
Figure 9: ULPI Timing Diagram
According to specification [5]:
TSETUPmax = 6 ns; THOLDmax = 3 ns But we don’t know how much our design is deviating from the given spec. It could be even greater than these limits. For a given link-PHY, setup and hold times are fixed. Values for set-up and hold were coming more than 6ns and 3ns respectively (Figure 9). So, the next challenge was to change the set-up and hold values which could not be attained through traditional method. It can only be changed if we change the controller (ultimately a re-spin!!!), which can be easily done by changing the code in FPGA [13] (cost effective method).
Figure 10: HS transmit differential data before debugging
So for the above explained approach we have included circuit as shown in figure 10 to reduce setup time in which we delayed the PHY-clock using buffer, cap & potentiometer and
One common 5V supply was used to generate different supplies for USBPHY block. After checking, it was concluded
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contributing in increased cycle time of a product. The proposed standalone validation framework is more robust and cost effective with reduced cycle time. It is capable of validating the micro-features of the USB specification [1]. FPGA based approach facilitates better control of negative stimulus for generation of error scenarios.
that all the supplies of 1.8V, 3.3V were coming proper. FS, LS transmitter and HS Receiver was working properly except HS transmit level were not proper causing eye failure. After debug on the standalone ULPI validation setup, it was found that by increasing around 500mv to one of the 1.8V (five 1.8V supplies in the design) supply, HS signals were reaching the required amplitude and HS eye diagram could be taken as shown in figure 11. This change in supply voltage could only be performed by standalone validation.
REFERENCES
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
Figure 11: HS transmit differential data after debugging
V.
[12]
CONCLUSION
[13] [14]
From the above case-studies we have observed that many issues escaping the traditional validation flow could be easily captured with the help of standalone validation method based on FPGA approach. It protects our SOC from customer issues
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USB 2.0 Specification, April 27, 2000. USB USB-IF USB 2.0 Electrical Test Specification Revision 1.03, Version 1.03, January 2005 at www.usb.org. USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.05, March 29, 2001. UTMI+ Specification, Revision 1.0, February 2, 2004 ULPI Specification, Revision 1.0, February 2, 2004 USB2.0 Transceiver and Macrocell Tester (T&MT) Interface Specification, Version 1.2 Universal Serial Bus Implementers Forum Full and Low Speed Electrical and Interoperability Compliance Test Procedure, version: 1.3 Universal Serial Bus Implementers Forum Host High-speed Electrical Test Procedure, version: 1.0 Universal Serial Bus Implementers Forum Device High-speed Electrical Test Procedure, version: 1.0 Embedded High-speed Host Electrical Test Procedure Revision 1.01 May 5, 2006 Paul D. Hale, Jeffrey Jargon, C. M. Jack Wang,Brett Grossman, Mathew Claudius, José L. Torres, Andrew Dienstfrey, and Dylan F. Williams, "A Statistical Study of De-Embedding Applied to Eye Diagram Analysis" published in IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 61, NO. 2, FEBRUARY 2012 Zhao Ren, Lizhong Gao, Bin CHANG, "Eye Diagram Construction and Analysis in Digital Phosphor Oscilloscope" published in 2010 International Conference on Intelligent Computation Technology and Automation. Ben Othman, Ben Salem, A.K.; Ben S FPGA-based drive controllers” IEEE Industrial Electronics (ISIE), 2010, pp.196-201. Alterra, http://www.altera.com/
