EE6250 VLSI Testing

NTHU EE

EE6250 VLSI Testing DFT Tutorial: Insert Scan Chain & ATPG Objectives: In this tutorial, you can learn: 1. How to insert scan chain into a your synthesized gate level design & run ATPG 2. The scan chain insertion flow as follow

Material: 1. Synthesized gate level verilog netlist of your design(e.g. GCD_syn.v) 2. Synopsys DFT Compiler setup file (same as Design Compiler). Define search paths, library name etc. Invoke DFTCompiler DFT compiler is actually embedded in the Design Compiler. To invoke DFT compiler, you can do either one % dc_shell –xg (command mode) % dv (GUI mode) Read input Files 1. Please check there is no error message when starting the “ design compiler”. If there are errors in the windows, please check the .synopsys_dc_setup. Type the command to read gate-level netlist of your design. % dc_shell read_file ./GCD_syn.v –format verilog

2. To obtain a timing/area report of your original design, type % dc_shell report _area > GCD_syn.area_rpt % dc_shell report _timing > GCD_syn.timing_rpt Step 1 Scan Ready Synthesis: Although you have done the synthesis before, you did not use the -scan option. This compilation considers the impact of scan insertion on mission mode constraints during optimization. This –scan option causes the command to replace all sequential elements during optimization. Type this command in your command lines. % dc_shell set_scan_configuration –style multiplexed_flip_flop % dc_shell set CLK_period 10 % dc_shell create_clock -name "clk" -period $CLK_period clk % dc_shell compile –scan Step 2 Set ATE configuration To create a test clock, type % dc_shell set_dft_signal -view existing_dft -type ScanClock -port clk –timing {50 100} To create a reset signal, type % dc_shell set_dft_signal -view existing_dft -type reset -port reset – active_state 0 To create a test default ports, type % dc_shell create_test_protocol Step 3 Pre-scan Check This command checks if your follow the gate-level scan design rule. Type % dc_shell dft_drc Step 4 Scan specification This command setup the dft compiler how many scan chains you want.Type % dc_shell set_scan_configuration –chain_count 1 Step 5 Scan preview This command checks your scan specification for consistency . Type % dc_shell preview_dft Step 6 Scan chain synthesis Stitch your scan elements into a chain. And some more optimizations. Type

% dc_shell insert_dft Step 7 Reports To obtain a timing/area report of your scan inserted design. Type % dc_shell report _area > GCD_dft.area_rpt % dc_shell report _timing > GCD_dft.timing_rpt Step 8 Write out files 1. To output your scan-inserted netlist. Type % dc_shell write –format verilog –hierarchy –output GCD_dft.v 2. To output your scan-inserted configuration file. This file is needed in next step, ATPG . Type % dc_shell write_test_protocol –output GCD_dft.stil 3. To output your scan-inserted standard delay format file(sdf). Type % dc_shell write_sdf -version 2.1 –context verilog GCD_dft.sdf

DFT Compiler to TeraMax

Invoke TetraMax TetraMax is used to perform ATPG (Automatic Test Pattern Generation) and fault simulation. Type the following command for invoke Tetramax % tmax –shell Read Netlist & Library Read scan inserted netlist file %build read_netlist Read library file %build read_netlist

gcd_dft.v tsmc18.v

–library

Reporting Modules -summary: Generate a summary report on all modules -error: Report all modules that have at least one violation of rule -undefined : Report all modules that are referenced but not defined $build report_modules -summary $build report_modules -error $build report_modules –undefined Building ATPG Design Model Builds the in-memory simulation model from the design modules that have been read in %build run_build_mode gcd Set DRC Parameters & Run Set the parameters that control DRC process. %DRC set_drc –allow_unstable_set_resets Perform Design rule checking %DRC run_drc gcd_dft.stil ATPG Create a list of faults for fault simulation and test generation. %TEST add_faults -all Set the parameters that control the ATPG processes -merge: specify whether to perform pattern merging during ATPG. The arguments indicates how much effort to spend doing merging -verbose: with –verbose enabled, extra messages are displayed during the pattern merge operation -abort_limit: specify the max. number of remade decisions before terminating a test generation effort during ATPG. -coverage: specify a test coverage limit at which to terminate the ATPG effort. -decision: when backtracking, using specific way to determine. %TEST set_atpg –merge high –verbose –abort_limit 250 –coverage 100 –decision random –fill x %TEST run_atpg Reporting Faults Sets the parameters that control the fault manager %TEST set_faults –summary verbose

Set which kind of fault you want to see collapsed/uncollapsed %TEST set_faults –report collapsed %TEST report_summaries Display fault Data -class: specifies a specific fault class to be reported -level [m] [n]: generates a fault report for specified hierarchical levels. The m argument specified the hierarchical depth of the report and the n specified a min. number of fault required to display a given depth %TEST report_fault –class UD %TEST report_fault –level 5 10 Writing Faults Write fault data to external file %TEST write_faults

gcd_fault.rpt

Write patterns to external file %TEST write_patterns

–all –replace

gcd_patterns.stil –format stil –replace