Three-Dimensional Space Vector Modulation for a ...

Three-Dimensional Space Vector Modulation for a Four-Leg Three-Level Inverter J.Yao

T.C.Green

Department of Electrical and Electronic Engineering Imperial College London London SW7 2BT, UK Tele: +44 (0)20 75946171 Fax: +44 (0)20 75946282 Email: [email protected], [email protected]

Keywords Multilevel converters, Modulation strategy, Distributed power

Abstract The trend toward deploying inverters in interfacing distributed generation (DG) systems to the grid has raised the importance of control and power quality aspects of inverters. Using multilevel inverters in DG systems, one can achieve high power quality outputs with realistic switching frequency. The four-leg three-level inverter topology is proposed for DG applications in three-phase four-wire systems, for its full dc link utilization and low voltage ripple on the dc link capacitors. A novel algorithm of three-dimensional space vector modulation (3D-SVM) is proposed for controlling a four-leg threelevel inverter. The issues of vector selection and switching sequence determination are described. Simulation results are compared with those of a three-leg three-level inverter to assess the effectiveness of the proposed 3D-SVM and to establish the advantages of the four-leg three-level topology over conventional three-leg three-level one.

Introduction In recent years, the number of power resources connected to power systems as distributed generation (DG) has increased. With the development of new generating techniques, such as photovoltaic arrays, variable speed wind turbines and fuel-cells, inverters are becoming more and more demanding to interface the power sources to the power systems. The trend toward deploying inverter interfaced distributed generation at medium/low voltage level has raised the importance of the control and power quality aspects of the inverter. For good quality waveforms a high control bandwidth is required and it is desirable to have large separation between the switching frequency and the passive filter’s cut-off frequency so the inductor can not be made too small. The problem is that the switching frequency is constrained by switching power loss and is most limited in high power devices. Thus there is a desire to raise the effective switching frequency of the inverter with a penalty in device losses. Multilevel inverter topologies have been proposed for medium and high voltage application because of the increase in system ratings. They also offer an effective switching rate higher than the rate of each device [1] and this might be useful in DG applications. Most low voltage DG systems will be required to supply unbalanced load in four-wire systems. To use a multilevel inverter in three-phase four-wire systems, a conventional approach is to connect the neutral point of the load to the midpoint of the dc link capacitors. In [2], [3], this approach is studied where the inverter was operating as an active power filter. However, although it is simple in terms of topology, this approach is not suitable for DG application, for the following reasons [4], [5]: 1) insufficient dc link utilization 2) high ripple on dc link capacitors 3) problem of dc link capacitor voltages balance. The four-leg topology has been shown to be a solution for inverters operating in three-phase four-wire systems, which offers full utilization of the dc link voltage and lower stress on the dc link capacitors [5].

This paper addresses the use of multilevel switching in four-leg inverters in order to produce the high effective switching rates needed for high power quality in DG applications. Space vector modulation has proved to be one of the most popular and favorable pulse width modulation schemes due to its high dc link voltage utilization, low output distortion, and ability to minimize the switching and conduction losses. With the development of digital signal processor (DSP), space vector modulation has another significant advantage of easy hardware implementation. In [4], [5], space vector modulation schemes are analyzed for a four-leg two-level voltage source inverter. In [6], [7], [8], space vector modulation schemes for multilevel inverters, including basic theory and optimized alternatives, are introduced. Authors in [2], [3] have presented a modulation scheme for a three-level inverter as an active power filter in three-phase four-wire systems where hysteresis modulation was designed in a three-dimensional domain. However, space vector modulation for a four-leg three-level inverter has not yet been studied. Thus a novel algorithm of space vector modulation for a four-leg three-level inverter is going to be proposed in this paper. The effectiveness of the proposed modulation algorithm, and the advantages of the proposed topology over conventional ones, are discussed and verified with simulation results.

Four-Leg Three-Level Voltage Source Inverters Three phase voltage source inverters usually have two ways of providing a neutral connection for three-phase four-wire systems[4]: 1) use of split dc link capacitors with the neutral connected to the mid-point of the capacitors 2) use of a four-leg converter with the neutral connected to the mid-point of the fourth leg With the former approach the three-phase converter becomes three independent single-phase converters, resulting in insufficient utilization of the dc link voltage. In addition, large dc link capacitors are needed to maintain an acceptable voltage ripple level in case of a large neutral current [5]. Thus the second approach is becoming more and more favoured, for its full utilization of dc link voltage and lower stress on dc link capacitors. The studies of multilevel inverters have been mostly based on the three-phase three-wire system topology because this is appropriate for balanced high voltage networks or balanced machine drives. To use a three-level inverter in a four-wire system, a conventional approach is to connect the fourth wire to the midpoint of dc link capacitors as shown in Fig 1. The drawbacks of using this simple neutral connection can be categorized as: 1) the incomplete utilization of dc link voltage 2) high ripple on the dc link capacitors caused by unbalanced or nonlinear load drawing high neutral current 3) dc link voltage unbalance caused by the large neutral current.

Sc1

S b1

Sc2

S b2

S a1

V DC1 VDC o

Load

S a2 L

a b c

V DC2

C Sc3

S b3

S a3

Sc4

S b4

S a4

R

n

Fig. 1.

The three-leg three-level inverter in three-phase four-wire system

This paper proposes a four-leg three-level inverter, which utilizes a fourth leg to provide the neutral connection. Fig 2 shows the proposed topology for a three-level inverter along with the output low pass filter and the load. The expected advantages of this topology are: 1) full utilization of dc voltage

S d1

Sc1

Sb1

S d2

Sc2

Sb2

S a1

V DC1 VDC

Load

S a2 L

a

o b d V DC2

c C S d3

S c3

Sb3

S a3

S d4

S c4

Sb4

S a4

R

Ln n

Fig. 2.

The proposed three-phase four-leg three-level inverter

(Voltages of 15% higher than using three-leg inverters can be generated based on the same dc sources.) 2) the additional leg can reduce the current flowing through dc link capacitors, resulting in lower voltage ripple and smaller dc link capacitors needed 3) the balance of dc link capacitors can be better controlled. In this four-leg switching network, the instantaneous ac terminal phase to neutral voltages vad , vbd and vcd can be expressed in terms of switching functions Sa , Sb , Sc and Sd , as well as dc link voltage VDC , assuming that VDC1 = VDC2 = VDC 2 .     Sa − Sd vad  vbd  =  Sb − Sd  · VDC (1) 2 Sc − Sd vcd The switching functions Sa , Sb , Sc three-level diode-clamped inverters.   2, 1, Sj =  0,

and Sd are defined as follows according to the characteristic of if Sj1 and Sj2 are closed if Sj2 and Sj3 are closed if Sj3 and Sj4 are closed

j = a, b, c, d

(2)

It can be observed from (1) and (2) that a three-level inverter of this topology can have output phase to neutral voltages with 5 levels rather than 3 levels with split capacitors approach. Thus it can be expected that a four-leg three-level inverter can generate output voltages with lower harmonic distortion compared with three-leg four-wire topology.

Three-Dimensional Space Vector Modulation For a Four-Leg Three-Level Inverter Space vector modulation (SVM) for three-level inverters have been studied for years. Because threelevel inverters are mostly used in three-phase three-wire systems where line to line voltages are concerned, SVM are then mostly based on two-dimensional space vectors [6], [7], [8]. 2D-SVM is sufficient if no neutral connection is needed, while 3D-SVM must be considered when a multilevel inverter is connected to a three-phase four-wire system providing neutral connection. In [2], [3], authors addressed the problem of SVM of a three-level inverter connected in a three-phase four-wire system, whose dc link capacitor mid-point was clamped to the neutral point to provide

a neutral connection. Hysteresis control based space vector selection in a three-dimensional domain was presented, for active power filter application. However, when the inverter is used as a distributed generation unit, hysteresis control based modulation schemes can not guarantee high quality voltage and current output. Moreover, the problem of dc link capacitor voltages balance should be investigated, because the three-leg four-wire topology along with the hysteresis control based modulation can generate prominent currents through dc link capacitors, resulting in high voltage ripple on dc link capacitors. Ideal capacitors are needed if this problem is not studied. A four-leg three-level converter can solve the above problems if proper modulation schemes can also be proposed. SVM for a four-leg inverter has been proposed for a standard two-level inverter [4]. It uses lookup tables to select switching states and corresponding duty cycles once the sector in which the reference vector falls has been identified. A similar modulation scheme can be applied to a four-leg three-level inverter, however the dimension and number of tables needed will increase dramatically as number of levels increases from 2 to 3, which can significantly decrease the efficiency of the modulation scheme. A more efficient SVM algorithm for four-leg three-level inverters will be proposed. The three phase to neutral voltage variables in (1) will be transformed to orthogonal coordinated α − β − γ domain using the following transformation equation:     Xα Xa  Xβ  = T ·  Xb  (3) Xγ Xc where the transformation T is defined as

 1 1 − √2 2 3 T = 0 2 3 1 1 2

 −√12 − 23 

(4)

1 2

2

Following a similar approach to that used for 3D-SVM for two-level inverters, the voltage vectors in 3D space will first be projected onto the 2D domain as shown in Fig 3. The triangle onto which the reference vector projects will be identified so that the corresponding nearest three switching vectors can be determined [7], [8]. In 2D-SVM for multilevel inverters, the switching sequence is optimized b

020

121 010

021

221 110

112 001

012

002

220

000 111 222

122 011

022

Fig. 3.

120

210

211 100

212 101

102

200

a

201

202

Voltage space vectors in α − β frame

to achieve low harmonic distortion as well as minimum switching losses. For example, if the sector is formed by vectors [1 0 0]([2 1 1]), [2 0 0] and [2 1 0] as shaded in Fig 3, the switching sequence can be as follows: [100] → [200] → [210] → [211] → [210] → [200] → [100] or [211] → [210] → [200] → [100] → [200] → [210] → [211]

Both of the above switching sequences are symmetrical to achieve low harmonic distortion [6]. Note that they will generate identical synthesized vector, thus the former one which starts with lower number switch state will be chosen in this paper. Also note that under this switching manner, each phase will have one switching transition in one half switching period, and reverse sequence in the next half switching period. The three nearest switching vectors and corresponding four switching states can be represented as rows of the matrix in (5), where x, y and z represent three phases while the mapping from a, b and c to x, y and z is different for each sector.   x y z x + 1 y z   S2D =  (5) x + 1 y + 1 z  x+1 y+1 z+1 Thus the general switching sequence on the α − β domain can be written as: [x, y, z] → [x + 1, y, z] → [x + 1, y + 1, z] → [x + 1, y + 1, z + 1] → [x + 1, y + 1, z] → [x + 1, y, z] → [x, y, z] Once the vector location has been done on α − β domain and the matrix of the form (5) is generated, the modulation can go further into three-dimensional space. The addition of the fourth leg gives the matrix in (6) which has three times as many possible states although only a subset will be used once the desired neutral voltage is defined. The objective of 3D-SVM scheme is to select five switching states from (6), which comply with the following rules: 1) the five switch states should represent four different vectors, 2) only one transition is allowed for each of the four legs in one half switching period. Under these rules the switching loss and switching frequency harmonics can be minimized.   x y z 0  x y z 1    x y z 2   x + 1  y z 0   x + 1 y z 1   x + 1 y z 2   S3D =  (6) z 0 x + 1 y + 1  x + 1 y + 1 z 1   x + 1 y + 1 z 2   x + 1 y + 1 z + 1 0   x + 1 y + 1 z + 1 1 x+1 y+1 z+1 2 The prism, corresponding to the identified triangle in α − β domain, formed by the 12 states in (6), is shown in Fig 4. The number i beside each point indicates ith state (row) in matrix (6). It can be observed from Fig 4 that there are six planes dividing the prism into seven tetrahedrons. These six planes are defined by three particular switching states respectively, which are: {1, 4, 7}, {1, 4, 8}, {1, 5, 8}, {2, 5, 8}, {2, 5, 9}, {2, 6, 9} where the numbers correspond to the numbers in Fig 4, representing the ith row in matrix (6). The reference voltage vector will be located in one of the seven tetrahedrons divided by the six planes. Since the six planes can be defined as mentioned above, the particular tetrahedron in which the reference vector falls and the corresponding five states, can be identified as illustrated in Fig 5. The numbers in brackets represent the selected states from Fig 4, ordered in a sequence that complies with the rules mentioned above.

(10)

4

(11) 1

5

(12) 2

6

7

8

9 3

Fig. 4. (10)

One of the sectors (Prism)

4

4

4 7

7

(11)1

(11)1

(11)1

5

8

Sector 1: [1 4 7 10 11]

8

Sector 2: [1 4 7 8 11]

(11)1

Sector 3: [1 4 5 8 11]

11

5

5

8 2

8 (12)2

Sector 4: [1 2 5 8 11]

Sector 4+: [2 5 8 11 12]

5

5 8

(12)2

(12)2

6

9

(12)2

6

9

9 3

Sector 5: [2 5 8 9 12]

Fig. 5.

Sector 6: [2 5 6 9 12]

Sector 7: [2 3 6 9 12]

The sub-sectors and corresponding switching states

Equation (6), Fig 4 and Fig 5 constitute a general algorithm to identify the position of the reference voltage vector, as well as to select the corresponding switching states for 3D-SVM for a four-leg three-level inverter. The procedure can be summarized as follows. 1) In the 2D domain, identify the triangle onto which the reference vector is projected hence the corresponding prism in 3D domain is identified. A matrix in the form of (5) can be generated. 2) Extend the matrix to the form of (6) and identify the six planes that divide the prism into tetrahedrons. 3) As illustrated in Fig 5, identify the particular tetrahedron in which the reference vector falls and select the corresponding switching states and sequence. Having identified the switching states and corresponding sequence as illustrated above, the five states representing four vectors can be selected from (6). Then the normalized duty cycles can be calculated using the following linear equations:     −1  tnorm1 α1 α2 α3 α4 αref tnorm2   β1 β2 β3 β4   βref       tnorm =  (7) tnorm3  =  γ1 γ2 γ3 γ4  ·  γref  tnorm4 1 1 1 1 1 £ ¤T £ ¤T where αi βi γi (i = 1, 2, 3, 4) are the selected switching vectors and αref βref γref is

the reference vector in α − β − γ domain, which is calculated by a transformation equation (3). The actual duty cycles can be calculated as t = Tsw · tnorm

(8)

where Tsw is the switching period, t and tnorm are the vectors of actual and normalized duty cycles respectively. Also note that the 1st and 5th switching states represent an identical vector, thus t1 is the combination of the 1st and 5th switching states. And the allocation of time between the 1st and 5th switching state gives another opportunity for control or balance purpose, which is not the concern in this paper.

Simulation Results and Comparison To investigate the performance of the proposed four-leg three-level inverter with the 3D-SVM, simulation results based on Matlab/Simulink/PLECS are shown in this section. The DC voltage is set to be 600V , the switching frequency is 2.5kHz and the load is a three-phase balanced resistor load. Moreover, for comparison purpose, simulations are also performed on a three-leg three-level inverter. All the spectra are generated by using Fast Fourier Transformation (FFT) on the sampled data. Fig 6 and Fig 7 are the step waveforms of the inverter phase to neutral voltages of a 3-leg 4-wire inverter and a 4-leg 4-wire inverter with 3D-SVM respectively. The waveform in Fig 7 has 5 levels 600

400

Voltage (V)

200

0

−200

−400

−600 0

Fig. 6.

0.005

0.01

0.015

0.02 0.025 Time (s)

0.03

0.035

0.04

Step waveform of the phase-neutral voltage with a 3-leg inverter

600

400

Voltage (V)

200

0

−200

−400

−600 0

Fig. 7.

0.005

0.01

0.015

0.02 0.025 Time (s)

0.03

0.035

0.04

Step waveform of the phase-neutral voltage with a 4-leg inverter and 3D-SVM

rather than 3 in Fig 6, resulting in lower harmonic distortion. The spectra of the corresponding voltages are shown in Fig 8 and Fig 9. It can be observed that the 4-leg 4-wire inverter can generate phase to neutral voltages with a maximum peak value of 0.577VDC , which is 15% higher than using a 3-leg 4-wire inverter. It is also shown that the switching frequency harmonics in Fig 9 are significantly lower than in Fig 8.

350

Voltage Peak Value (V)

300

250

200

150

100

50

0 0

50

100

150

200

Order of Harmonics

Fig. 8.

Spectrum of phase-neutral voltage with 3-leg inverter 350

Voltage Peak Value (V)

300

250

200

150

100

50

0 0

Fig. 9.

50

100 Order of Harmonics

150

200

Spectrum of phase-neutral voltage with 4-leg inverter and 3D-SVM

The simulation results and discussion above indicates that a four-leg three-level inverter can generate a phase to neutral voltage with significantly lower switching frequency harmonics. It can also generate 15% higher phase to neutral voltages than a three-leg three-level inverter.

Conclusions A four-leg three-level inverter is proposed for application in distributed generation or active power filter, where a neutral connection is needed for a three-phase four-wire system. A four-leg three-level inverter can fully utilizes the dc link voltage and generate lower distortion for a given switching rate. To exploit the four-leg three-level inverter a three-dimensional space vector modulation has been designed which is based on an efficient algorithm. For three-level inverters, the modulation algorithm is based on a 12 × 4 matrix and eight selecting vectors, which is much more efficient compared with using look-up tables for vector selections. Simulation to analyze the performance of the four-leg three-level inverter and proposed 3D-SVM is shown, compared with those with a three-leg three-level inverter with neutral connection. Comparison and discussion show that the proposed topology along with the modulation algorithm can achieve better performance in terms of dc link utilization and harmonic distortion. R EFERENCES [1] J.Rodriguez, J.Lai and F.Peng “Multilevel Inverters: A Survey of Topologies, Controls and Applications”, IEEE Trans. on Industrial Electronics, 49(4), pp.724 -738, August 2002. [2] Man.Wong, J.Tang and Y.Han “Three-Dimensional Pulse-Width Modulation Technique in Three-level Power Inverters for Three-Phase Four-Wired System”, IEEE Trans. on Power Electronics, 16(3), pp.418 -427, May 2001. [3] Man.Wong, J.Tang and Y.Han “Cylindrical Coordinate Control of Three-Dimensional PWM Technique in Three-Phase Four-Wire Trilevel Inverter”, IEEE Trans. on Power Electronics, 18(1), pp.208 -220, January 2003.

[4] R.Zhang, V.H.Prasad, D.Boroyevich and F.C.Lee “Three-Dimentional Space Vector Modulation for Four-Leg VoltageSource Converters”, IEEE Trans. on Power Electronics, 17(3), pp.314 -326, May 2002. [5] R.Zhang, D.Boroyevich and V.H.Prasad “A Three-Phase Inverter with A Neutral Leg with Space Vector Modulation”, Applied Power Electronics Conference and Exposition, 1997, pp.857 -863, February 1997. [6] B.P.McGrath, D.G.Holmes and T.Lipo “Optimized Space Vector Switching Sequences for Multilevel Inverters”, IEEE Trans. on Power Electronics, 18(6), pp.1293 -1301, November 2003. [7] J.H.Seo, C.H.Choi and D.S.Hyun “A New Simplified Space-Vector PWM Method for Three-Level Inverters”, IEEE Trans. on Power Electronics, 16(4), pp.545 -550, July 2001. [8] N.Celanovic and D.Boroyevich “A Fast Space-Vector Modulation Algorithm for Multilevel Three-Phase Converters”, IEEE Trans. on Industry Application, 37(2), pp.637 -641, March/April 2001.