ASIC by Design - Automated design of digital signal ...

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Automated Design of Digital Signal Processing Application-Specific Integrated Circuits

Modeling the Scaling Limits of Double-Gate MOSFETs Don Bouldin, Warren Snapp, Paul Haug, David Sunderland, with Physics-Based Compact Short-Channel Models of Roger Brees, Carl Sechen, and Wayne Dai Threshold Voltage and Subthreshold Swing

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IEEE CIRCUITS & DEVICES MAGAZINE

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JULY/AUGUST 2004

architecture, logic, circuit, and physical layout design. EDA tools with scripts provided by the vendors are not yet able to match the custom design team in dealing with these issues. Furthermore, custom designers can utilize nonstandard logic families, such as high-speed dynamic logic or clockless logic, even if these are not generally supported by available EDA tools. Physical design can be highly optimized in custom designs with manual polygon pushing to squeeze every micron of density out of the process. This higher density translates into higher performance. Because of high prototyping costs and tight schedules, ASIC designs must work on first-pass and, hence, are often derated or deoptimized to provide safety margins allowing for inexactly modeled timing and noise issues. The net result is that ASICs typically suffer from roughly a 10× reduction in optimization as measured in clock speeds, power, and area, relative to full custom integrated circuits [1]. Even advanced synthesis techniques provide only 2–4× improvement over traditional methodologies and certainly cannot achieve the desired 10×. The project described in this article has the objective of developing and demonstrating a new ASIC design technique that will close the performance gap between full custom and traditional ASIC methods. As shown in Figure 2, the project is concerned only with ASICs that are dominated by DSP with less than 5% of the area being consumed for control. Optimization of memory is outside the scope of this project.

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pplications requiring cost-effective, low-power digital signal processing (DSP) are prevalent not only in military and aerospace systems but also in numerous commercial products. Many of these systems need to be miniaturized so they can be highly mobile or portable. The resulting severe size, weight, and power requirements for DSP electronics can only effectively be realized in the form of advanced application-specific integrated circuits (ASICs) implementing mission-specific architectures. As shown in Figure 1, mission-specific ASIC architectures can realize 100× improvement in giga operations per second per watt (GO/s/W) for a typical DSP algorithm versus implementation in general purpose DSP chips [1]. (An operation is defined by most ASIC designers as a 16 × 16-b multiplication. However, this definition is not universal, so in this article we report improvements normalized to a baseline to factor out this term.) Programmable logic chips are insufficient to achieve the desired throughput and power specifications for these applications. Unfortunately, there is a problem that currently blocks designers from implementing these ASICs cost effectively. ASICs are typically designed by small design teams using highly automated logic, circuit, and physical synthesis electronic design automation (EDA) tools. By contrast, standard high-volume products are designed by large teams of specialists using more manual or “full custom” methods. Custom designers perform a high degree of optimization at all levels, including

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achieved, synthesizing the HDL with mapping to a standardcell library, and then physically placing and routing with clock tree insertion to produce the layout. Of course, post-layout simulation and other verification techniques (design rule checks, noise analysis, etc.) are also performed. ASIC designers use scripts to provide guidelines and constraints to EDA tools to achieve the desired power, delay, or area goals of a given function or macro. EDA vendors provide basic scripts, but it is up to the designers to learn the tools and their many options to determine which options to select. Hence, the results presented below are compared to the basic scripts that produce a baseline layout for the DSP macros we considered. The baseline flow invoked Synopsys Boeing Design Compiler [2] for synthesis in its STAP ASIC Equivalent Array of 120 Tiger SHARC DSPs default mode and Cadence Silicon Ensem(200 GO/s/W) (