You will get an introduction to DFT (design for test) by inserting a scan chain into
... Synopsys uses DFT Compiler to insert scan chains into the design. There are ...
Instructions for
Lab 3: Advanced ASIC Design Flow SMD154 VLSI Design
SMD154 VLSI Design
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SCAN CHAIN ......................................................................................................3 1.1
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CHECKING THE SCAN CHAIN...........................................................................5 SUBMISSION 3B ...............................................................................................6
LAB ASSIGNMENT 3C......................................................................................6 4.1 4.2 4.3 4.4 4.5
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CHECKING YOUR SCAN CHAIN .......................................................................4 SUBMISSION 3A ...............................................................................................4
LAB ASSIGNMENT 3B......................................................................................5 3.1 3.2
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SCAN CHAINS AND DESIGN FOR TEST .............................................................3
LAB ASSIGNMENT 3A......................................................................................4 2.1 2.2
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Lab 3: Advanced ASIC Design Flow
DESIGN ENTRY ...............................................................................................6 FRONTEND - CHANGED CLOCK FREQUENCY ...................................................7 BACKEND ........................................................................................................7 VERIFY ...........................................................................................................8 POST LAYOUT SIMULATION ............................................................................8
APPENDIX.........................................................................................................10
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SMD154 VLSI Design
Lab 3: Advanced ASIC Design Flow
1 Scan Chain 1.1 Scan Chains and Design for Test In this lab you will continue to work with your ALU design from lab 2. A simple directory structure (with a modified test bench) can be found at /digcad/smd154/2006/lab3/lab3.zip. You will get an introduction to DFT (design for test) by inserting a scan chain into your design and see which fault cover you can reach. A common technique used for DFT (design for test) is an internal scan chain. Complex sequential blocks are partitioned in either isolated combinational blocks (full-scan design) or partially isolated combinational blocks (partial-scan design). By extending the flip-flops with support for serial shift (compare DFC1 with DFSEC1); it is possible to chain the flipflops together to form a scan-chain (Figure 1).
Figure 1. Example of a design without and with a scan chain.
Synopsys uses DFT Compiler to insert scan chains into the design. There are a few different scan methods available and the one used in this lab is called multiplexed flip-flop (Figure 2). A drawback with this method is that the performance of the circuit is decreased. In short, the multiplexed flip-flop scan style uses a multiplexed data input to provide serial shift capability. During functional mode, the scan-enable signal, acting as the multiplexer select line, selects the system data input. During scan shift, the scan-enable signal selects the scan data input. The scan data input comes from either the scan input port or the scan output pin of the previous cell in the scan chain.
Figure 2. Multiplexed flip-flop scan cell.
Read more about scan chains in chapter 14.6 in Smith, Application-Specific Integrated Circuits (http://www.edacafe.com/books/ASIC/Book/CH14/).
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SMD154 VLSI Design
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2 Lab assignment 3a This lab is an introduction to DFT flows for designs in the logical domain, thus we will only use Design Compiler and Synopsys DFT compiler. In this lab assignment 3a, use the same vhdl-files as in the previous lab, and feel free to reuse the same script for logical synthesis as you used before. Please see Appendix for using the command sequence provided, where you can take a design from an HDL-level circuit description (without existing scan) to a fully optimized design with internal scan circuitry.
2.1 Checking Your Scan Chain Fault coverage is a method to define testability of a design and shows to what extent the design can be checked for manufacturing defects. Fault coverage is defined as fault coverage = detected faults / detectable faults Read more in chapter 14.1 and 14.1 in Smith, Application-Specific Integrated Circuits (http://www.edacafe.com/books/ASIC/Book/CH14/). As noted in the appendix, you use the command estimate_test_coverage to check your fault coverage and use the command dft_drc to check your design against the design rules for multiplexed flip-flop. You should not have any (dft) violations in assignment 3a.
2.2 Submission 3a As indicated in the script in the appendix, after the scan insertion, you need to perform design rule checking again to ensure no violations have been introduced into your design by the scan insertion process. More specifically, you execute and save in a text file (lab3a.txt) the results of the commands: # Check that you have satisfied the constraints report_constraint -all_violators -verbose # Recheck the test design rules dft_drc # Report scan path report_scan_path -view existing_dft -chain all # Check test coverage statistics on the current design estimate_test_coverage # Report max/min delay report_timing -path full -delay min report_timing -path full -delay max
In the same text file, answer the following questions (info can be found by the generated report above): 1. 2. 3. 4.
What is your max and min slack? What is the length of the scan path? What is the test coverage (%)? You should not have any design rule violations, but in this state, you might have timing problems (if so given by the report_constraint command). If you have timing violations, please explain as good as you can why Synopsys report violations.
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SMD154 VLSI Design
Lab 3: Advanced ASIC Design Flow
3 Lab assignment 3b You should now discard the naive VHDL model of the SRAM that was given in lab 2 since it takes to long time to synthesize (that is why its size was only 16x8 bits) and, more important, it does not use real estate (chip area) efficiently. Instead you will use an IP block that has been pre-generated by a memory compiler from AMS (the interested can find more information at http://asic.austriamicrosystems. com/databooks/digital/). The size of the new SRAM is 128x8 bits. You should replace the src/sram.vhd file with the sram128x8 block. In effect, it is done already by the given .synopsys_dc.setup that adds the path to the sram128x8.db. However, you need to modify alu.vhdl slightly to instantiate sram128x8 instead of the vhdl-file and change the number of address bits to the memory. (Note: The timing diagram for the pre-generated memory differs from the one provided in lab 2. In lab assignment 3b, ignore the discrepancy. For now, it is only required to change the address bits and component to instantiate). You should then be able see to use the same command sequence provided in appendix, where you can take a design from an HDL-level circuit description (without existing scan) to a fully optimized design with internal scan circuitry. (Remember: Do not analyze src/sram.vhd. in lab assignment 3b!)
3.1 Checking the Scan Chain Use the command dft_drc to check your design against the design rules for multiplexed flip-flop. Unfortunately, the three state buffers used by the IP block causes violations. ----------------------------------------------------------------Begin Topology violations... Warning: Three-state net alu0/Q_i[7] is not properly driven. Information: There are 7 other nets with the same violation. Topology violations completed... -----------------------------------------------------------------
It is possible to work around this problem using Shadow LogicDFT to create a wrapper around the memory. However, we accept these violations in this lab. Thus, your report will likely look something like this: ----------------------------------------------------------------DRC Report Total violations: 9 ----------------------------------------------------------------1 MODELING VIOLATION 1 Cell has unknown model violation (TEST-451) 8 TOPOLOGY VIOLATIONS 8 Improperly driven three-state net violations (TEST-115) Warning: Violations occurred during test design rule checking. ----------------------------------------------------------------Sequential Cell Report 0 out of 75 sequential cells have violations ----------------------------------------------------------------SEQUENTIAL CELLS WITHOUT VIOLATIONS * 75 cells are valid scan cells
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SMD154 VLSI Design
Lab 3: Advanced ASIC Design Flow
3.2 Submission 3b As indicated in the script in the appendix, after the scan insertion, you need to perform design rule checking again to ensure no violations have been introduced into your design by the scan insertion process. More specifically, you execute and save in a text file (lab3b.txt) the results of the commands: # Check that you have satisfied the constraints report_constraint -all_violators -verbose # Recheck the test design rules dft_drc # Report scan path report_scan_path -view existing_dft -chain all # Check test coverage statistics on the current design estimate_test_coverage # Report max/min delay report_timing -path full -delay min report_timing -path full -delay max
In the same text file, answer the following questions (info can be found by the generated report above): 1. 2. 3. 4.
What is your max and min slack? What is the length of the scan path? What is the test coverage (%)? If the test coverage differs from assignment 3a, please explain as good as you can why there is a difference. 5. You should not have any design rule violations, but in this state, you might have timing problems (if so given by the report_constraint command). If you have timing violations, please explain as good as you can why Synopsys report violations.
4 Lab assignment 3c In this lab assignment, we will use the IP block that has been pre-generated by a memory compiler from AMS and incorporates the block into the ALU and take the design through the entire design flow. In lab assignment 3c, you don’t have to insert scan chains into the design.
4.1 Design Entry As in assignment 3b, you should replace the src/sram.vhd file with the sram128x8 block. As mentioned, the timing diagram for the pre-generated memory differs from the one provided in lab 2, which means that you might have redesign your ALU slightly. The timing diagram for the pre-generated memory can be found at http:// asic.austriamicrosystems.com/databooks/digital/mc_spram_c35_timing.ht ml.
4.1.1 RTL Simulation Remember to compile the new memory file when simulating your design. When simulating the design at RTL, use the sram128x8_func.v (that has disabled timing checks) e.g. do: 6(10)
SMD154 VLSI Design
Lab 3: Advanced ASIC Design Flow
ncvlog /digcad/smd154/2006/lab1/sram128x8/sram128x8_func.v
instead of ncvhdl sram.vhdl.
4.2 Frontend - Changed Clock Frequency When the ALU is operated at a clock frequency of 100 MHz, the CMOS technology is far from pushed to its limit. However, in this assignment, we decrease the clock frequency to 60 MHz instead. The rationale is that you might get hold-time violations in your design, so when performing optimization, you can focus on fixing the hold problems. You have to make changes in the following files: • Syntesis script1: Create clock with the new period to reflect your frequency. • Syntesis script2: Change the operating conditions, as max condition, set WORST from the c35_CORELIB (instead of WORST-MIL as in lab 2). • check_layout.tcl: Change the FREQUENCY variable.
4.3 Backend The following settings have to be modified for Encounter: • c35b4_std.conf: Add path to sram block: tlf: /digcad/smd154/2006/lab1/sram128x8/sram128x8_43.tlf lef: /digcad/smd154/2006/lab1/sram128x8/sram128x8.lef
Some hints on gemma.tcl. You have to add commands for placing the memory block, create power rings, and cutting rows around it. •
UPDATE! It seems like the generated layout script generates a lot of violations when adding periphery cells. So before routing the pad ring (“srouting” gnd3o! gnd3r! vdd3o! vdd3r2! vdd3r1!), execute the fillperi.tcl script. E.g. the simplest way seems to be: add core rings, block rings, and stripes as usual, then: > source fillperi.tcl > sroute -jogControl {preferWithChanges differentLayer}
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to connect all power and ground rings, block pins, pad pins, pad rings, stripes, etc. Then continue with placement of standard cells as usual. Should you have large timing violations, consider a lower core utilization when initializing the floorplan (e.g. by testing going from 85% -> 75 %) Place the memory block. (help modulePlace) Set block status to “fixed” and add a halo to the block, use: > setBlockPlacementStatus -allHardMacros -status preplaced > addHaloToBlock 20 20 20 20 -allBlock –fromInstBox
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Cut rows under macros, halos and blockages, use > cutCoreRow Add power and ground rings around the memory block. Use (almost) the same settings as in lab 1, i.e. width 4, spacing 1 etc. for the nets gnd! and vdd!. However, in this lab we increase the Offset, (the distance in microns between
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SMD154 VLSI Design
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Lab 3: Advanced ASIC Design Flow
the edge of the inner ring and the boundary of the referenced block), specify an offset of 4 otherwise we might get DRC violations. You can clear the design with the command freeDesign should you want to start over again. If timing and/or constraints are not meet, it is time to re-optimize the design. Have a look at the optDesign command if needed (or runPhySyn command. The recommended reading is the section Synthesis Optimization in the timing manual/menu if you perform post placement optimization after generating the clock tree).
4.4 Verify Ideally, the route design should not result in any violations. Run violation reports for the connectivity and geometry. Currently, the only allowed violations are related to the VDD and GND pads as in lab2. Finally, extract the setload and setres files as done in lab 2 (converting to tclcommands using transcript). Run the (modified) script check_layout to generate the SDF file for post-layout simulation. Note: If you get violations you are uncertain about, contact the lab assistance for … assistance.
4.5 Post Layout Simulation When simulating the routed design, use the sram128x8.v (with timing checks) e.g: (assuming running from a directory parallel with a “par” directory) ncsdfc ncvlog ncvlog ncvlog ncvlog ncvlog ncvhdl ncelab
-output ./top.sdf.X top.sdf /digcad/hk_3.70/verilog/udp.v /digcad/smd154/2006/lab1/sram128x8/sram128x8.v /digcad/hk_3.70/verilog/c35b4/c35_IOLIB_4M.v /digcad/hk_3.70/verilog/c35b4/c35_CORELIB.v ../par/EXPORTS/top_routed.v -v93 ../src/top_tb.vhd -v93 -ACCESS +r -messages -neg_tchk -nowarn cuvwsp –nowarn \ sdfndp -nowarn sdfinf -nowarn sdfuncon -timescale "1ns/10ps" \ worklib.top_tb:sim -sdf_cmd_file SDF_command
4.5.1 Submission 3c Besides taking your ALU through the ASIC design flow, you should also report the timing at various stages as in lab2. You should pass the timing check and not have violated any constraints. The slack from report timings commands should be met (positive). Prepare to take notes and report on both the setup and hold time analysis (6 values in total): A) When the design is synthesized. B) When the design is routed. C) When the design is back-annotated. The files needed for submission are: A) The final netlist from layout
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B) The generated sdf file from post-layout (generated by Design Compiler). The 2 files makes it possible to verify the functionally of your design (at least to run the simulator with some simple test cases). C) The routed layout, e.g. the file top.enc and the directory top.enc.dat. Send an e-mail with the attached files (remember the text files from submission 3a, 3b) no later than the submission date as posted on the web page.
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SMD154 VLSI Design
Lab 3: Advanced ASIC Design Flow
5 Appendix The following changes should be done to your top.tcl (or the name of the file you used in lab2). #---------------------------------------------------------------------# Inserting scan chains into the design. # # Commands are given. # Please note the -scan flag on the compile command #---------------------------------------------------------------------# Read in files as in lab2 # For 1st run, read in sram.vhdl # For 2nd run, don’t read in sram.vhdl, use the sram128x8 memory block. # NOTE! Remember to modify alu.vhd to instantiate sram128x8 instead! # Set design environment and constraints as in lab2, then: # Set up for design rule checking on the RTL source. set hdlin_enable_rtldrc_info true # Select the scan style, the scan style is multiplexed flip-flop. set test_default_scan_style multiplexed_flip_flop # Define clocks and asynchs in your design, then generate a test protocol. create_test_protocol -infer_clock -infer_async # Check test design rules in the RTL source file using RTL Test DRC dft_drc # Synthesize a design that meets the constraints you set, and map your # circuit, description to cells from the target technology library. # Because of the –scan option, all flip-flops in the design are implemented # as scan flip-flops. compile -scan # Post-Processing the design report_constraint -all_violators # Again, check the test design rules. (At this stage, DFT Compiler checks # for and describes potential problems with the testability of your design). dft_drc # Building Scan Chains. When you add scan-test circuitry to a design, its # area and performance change. DFT Compiler minimizes the effect of adding # scan-test circuitry on compile design rules and performance by using # synthesis routines. insert_dft # Check that you have satisfied the constraints report_constraint -all_violators -verbose # Recheck the test design rules dft_drc # Report scan path report_scan_path -view existing_dft -chain all # Check test coverage statistics on the current design estimate_test_coverage # Report max/min delay report_timing -path full -delay min report_timing -path full -delay max
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