2012 5th International Conference on BioMedical Engineering and Informatics (BMEI 2012)
A 16-bit Carry Skip Adder Designed by Reversible Logic Yu Pang Chongqing University of Posts and Telecommunications, Chongqing, China
[email protected]
Junchao Wang Chongqing University of Posts and Telecommunications, Chongqing, China wangjunchao1990@hotmai l.com
Abstract- In digital integrated circuit designing, energy dissipation has become a crucial factor which engineers would consider before they begin the design. However, irreversible computing is one of the most significant factors of energy dissipation. Therefore, designing digital circuits by reversible logic way is an efficient way to decline the energy dissipation of the circuit. In this paper, we proposed a 16-bit carry skip adder which is an optimization of traditional ripple carry adder designed by reversible logic. Keywords: Reversible logic, Carry skip adder, TOFFOLI gate, CNOT gate, Quantum cost
I.
Shaoquan Wang Chongqing University of Posts and Telecommunications, Chongqing, China
[email protected]
The synthesis of reversible logic relies on basic reversible gates such as TOFFOLI family illustrated in Fig. 1. The gates with 1 or 2 inputs are called NOT, and CNOT, and correspond to TOF1(A) and TOF2 (A, B). A gate with three inputs is referred to as a TOFFOLI gate, and is represented by TOF3(A, B, C). Note, that in Fig. 1, all added output bits P and Q are garbage bits while R is the information bit [3].
INTRODUCTION
With the development of integrated circuits, researchers concern more and more about the energy dissipation of the circuits. However, irreversible logic computing is one of the most crucial factors of energy dissipation, which can be illustrated by the Landauer’s principle [1] - each bit of information lost will generate kTln2 joules of heat energy, where T stands for absolute temperature at which computation is performed and k is Boltzmann’s constant. Therefore, designing integrated circuits by reversible logic way can preserve certain amount of energy dissipation. The reversible logic is based on the concept of bijective Boolean functions, where the output vector is a permutation of all the input combinations [2]. Therefore, input vector states can be always uniquely reconstructed from the outputs. A non-reversible specification has typically a different number of inputs and outputs, that is, f:Bn Bm. In order to guarantee a bijective mapping, the input size must be equal to the output count, the additional inputs or outputs must be often used to generate a reversible embedding of an irreversible function fr. Such additional inputs are called ancilla bits, while extra outputs are referred to as garbage bits (g).
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(a)
(b)
(c)
Fig. 1. Basic reversible gates
Adders are one of the most common elements in digital circuit design since addition is a fundamental operation for any kind of digital systems. However, traditional ripple carry adders have some defects such as low computing efficiency and long delay. In order to overcome the disadvantages above, a new kind of adder called Carry Skip Adder (CSA) which has shorter delay has been proposed. In this paper, we present a new design of 16 bit CSA which can both enhance the computing efficiency and decline the amount of energy dissipation based on reversible logic theory. Since wireless sensor networks need very low power devices, the computational units consisting of the proposed adder can satisfy the requirement.
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Fig. 2. Circuit scheme of the 16-bit CSA
II.
BACKGROUND OF CSA
Traditional CSA is an optimization of ripple carry adder (RCA) which decreases the computing time [4]. As is shown in Fig. 2, a 16-bit CSA which can be constructed by four parts of 4-bit CSA has 32-bit inputs (A0 – A15 and B0 –B15) and 17-bit outputs (S0 – S15 and Co16). Each 4-bit CSA contains a 4-bit RCA, a comparison block and a MUX. If the two inputs in one 4-bit CSA, for instance, A4 – A7 and B4 – B7 in the second 4-bit CSA, are completely reverse, then the carry entering the CSA will simply be propagated to the next 4-bit CSA so there is no need for the next CSA to wait for the carry-in created by this current 4-bit CSA. Therefore, the delay mainly generated by the carry bit can be shortened. In each comparison block both input bits are compared for un-equivalence [5][6][7]. This is done by Exclusive ORing each individual cell (parallel operation) which produces a comparison string. Next the comparison string is ANDed within itself in a domino fashion. This process ensures that the comparison of each and all cells is indeed unequal and we can, therefore, proceed to propagate the carry to the next block. For example, the comparison block performs the calculation for the second 4-bit CSA as (A4⊕B4)●(A5⊕B5)●(A6⊕B6)●(A7⊕B7). A MUX is responsible for selecting a generated carry or a propagated (previous) carry with its selection line being the output of the comparison circuit just described. If each 4-bit CSA block Ai≠Bi then we say that a carry can skip over the block. Otherwise, if Ai = Bi we shall say that the carry must be generated in the block. For example, we get two random strings that are shown in Fig. 3. As mentioned above, two groups of 16 bit binary number strings are divided into 4 parts, then they enter to 4 comparison blocks(block 0 to 3) respectively. Since in block 0 those 2 pairs of 4 bit numbers are not completely reverse, the carry skip mechanism would be unable to skip the block which means the carry would
be generated as traditional RCA. The situations in block 2 and block3 are the same as block 0. However,
Fig.3 .Two random strings the two pairs of 4-bit binary numbers are completely reverse in block 1, so the carry-in of this block would simply be propagated to the next block without computing. This carry skip mechanism shortens the length of delay of computing the carry of this block.
III.
PROPOSED REVERSIBLE LOGIC 16-BIT CSA
Using reversible logic to re-design a 16-bit CSA needs to transform each block in Fig. 2 into a reversible block [8][9][10][11]. In this section we describe the reversible structures for the 4-bit RCA, comparison block and MUX [12][13]. Since the basic element of a 4-bit RCA is the full adder, we first re-design it by reversible logic shown in Fig. 4 (a). The circuit consists of three CNOT gates and two TOFFOLI gates with two ancilla bits in five inputs. However, observing the first full adder in each 4-bit RCA in Fig. 2 finds that the carry-in should be given to the full adder and MUX concurrently which violates the rule of prohibited fan-in, so the Fig. 4 (a) is amended to the Fig. 4 (b) which adds a CNOT gate representing the first full adder in each 4-bit RCA. Then we design the comparison block illustrated in Fig. 5 with 11 inputs comprising three ancilla bits. This reversible circuit consists of four CNOT gates and three TOFFOLI gates. The output “D” performs the function D=(A3⊕B3)●(A2⊕B2)●(A1⊕B1)●(A0⊕B0). If all Ai ≠B i, D will generate the value “1”. The q u a n t u m c o s t i s calculated as 4*1 + 5*3=19.
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(a)
(b)
Fig.4. The reversible logic full adders
Fig.5. The reversible circuit of the comparison block
Fig. 7. Scheme of the reversible 4-bit CSA
The MUX block carries out the function as Co 4 n = Cin • D ⊕ Co[3 + 4( n − 1)] • D where D comes from the comparison block and Co[3+4(n-1)] comes from the last reversible full adder in the 4-bit RCA. Its reversible design is illustrated in Fig. 6 which has a CNOT gate and two TOFFOLI gates. After connecting all the reversible blocks described in Fig. 4 – 6, we can obtain the reversible circuit of 4-bit CSA which utilizes 18 CNOT gates and 13 TOFOLLI gates totally with quantum cost 83. Fig. 7 describes the scheme of reversible 4-bit CSA. As long as cascading four 4-bit reversible CSA, the 16-bit reversible logic CSA is obtained. Therefore, the 16-bit reversible CSA has 72 NOT gates and 52 TOFFOLI gates with total quantum cost 332.
Fig. 6. The reversible logic circuit of MUX
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IV.
EXPERIMENTAL RESULTS
To verify the correctness of the proposed adder, we use VHDL to program the reversible logic 16-bit CSA. All experiments are performed in Xilinx ISE 10 in a 2048MB, 2.4GHz Intel Core2 machine under Windows7. The experimental results are summarized in Fig. 8.
Fig. 8. Experimental result for reversible 16-bit CSA
We get five couples of 16 binary digits randomly first. Each of them is a group of experimental data, one is for A inputs, the other is for B inputs. The column of “A” denotes the data of nodes A inputs illustrated by decimal numeral, while the column of “B” stands for B. The column of “S” indicates the results of various inputs data respectively, and the column of “Co15” is the carry out of the adder. Therefore, the functions of reversible 16-bit CSA are regular and the proposed design is successful. On the other hand, in order to justify the length of the delay of the proposed 16-bit reversible CSA can be shortened compared with traditional RCA, we also perform an experiment to observe the delay of both adders. The results of this experiment are illustrated in Table 1. Area (slice) Delay (ns) Ripple carry adder 8 110.5 Carry skip adder 13 90.3 Carry select adder 17 67.1 Table 1. Area and delay comparison between three 16-bit adders
Table 1 shows the comparison of area and delay between the ripple carry adder, carry skip adder and carry select adder which all perform 16-bit addition. Obviously, ripple carry adder has the smallest area but the largest delay, while the carry select adder has the smallest delay but the largest area. The carry skip adder balances the two important indicators of area and delay in circuits, so this type adder is used widely in digital circuit design. V. CONCLUSION Carry-skip adder has the advantage of short delay and high computing efficiency so causes wide attention. In this paper, we propose a new design of 16-bit CSA based on reversible logic which consists
of 72 CNOT and 52 TOFFOLI gates with total quantum cost of 332. This adder designed by reversible logic has obvious advantages of short delay and low power dissipation, so it can be applied to wireless sensors very well.
Acknowledgments
The research reported herein was sponsored largely by the National Natural Science Foundation of China under the grant No. 61102075, and by the Natural Science Foundation of Chongqing under the grant No. CSTC 2011BB2142 and No. KJ120507. Reference [1] R. Landauer. Irreversibility and heat generation in the computing process. IBM J. of R&D, 5:183–191, 1961. [2] Bruce J W, Thronton M A, Shivakumaraiah L, Kokate PS, Li X (2002), "Efficient adder circuit based on a reversible conservative logic gate", IEEE Computer So ciety Annu al S ympo sium o n V LS I.pp.2 . [3] Yu Pang, Shaoquan Wang, Zhilong He, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka, "Positive Davio-based Synthesis Algorithm for Reversible Logic". 2011 IEEE 29th International Conference on Computer Design (ICCD).pp. 212. [4] Alain Guyot, Bertrand Hocheft, Jean-Michel Muller."A Way to Build Efficient Carry-Skip Adders". IEEE Transactions on Computers, Oct. 1987. pp. 1144-1145. [5] Chirca, K. , "A static low-power, high-performance 32-bit carry skip adder", Euromicro Symposium on Digital System Design, 2004. DSD 2004. pp.1-4. [6]Yu Shen Lin, "Delay Efficient 32-bit Carry-Skip Adder", IEEE International Conference on Electronics, Circuits and Systems, 2006. ICECS '06. 13th. pp. 506-507. [7] Burgess, N. ,"Accelerated carry-skip adders with low hardware cost". Conference on Signals, Systems and Computers, 2001. pp. 852-853. [8] Yu Pang; Jinzhao Lin; Sultana, S.; Radecka, K., "A novel method of synthesizing reversible logic", 2011 IEEE International Symposium on Circuits and Systems (ISCAS).pp. 2857-2858. [9] Sayeeda Sultana and Katarzyna Radecka “Reversible Adder/Subtractor with Overflow Detector”. 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS). pp. 1-2. [10] L. Ni, Z. Guan and W. Zhu, "A General method of Constructing the Reversible Full Adder", 3rd Inti. Symp. on Intelligent Inf. Technology and Security Informatics, pp. 109-113,2010. [11] Bruce, J.W. ,"Efficient adder circuits based on a conservative reversible logic gate ", Symposium on Proceedings. IEEE Computer Society Annual. VLSI, 2002. pp. 3-5. [12] Thapliyal, H. Ranganathan, N. “A new reversible design of BCD adder”, Design, Automation & Test in Europe Conference & Exhibition, 2011. pp. 1-3. [13] Marek Perkowski, Martin Lukac, Dipal Shah, Michitaka Kameyama, “Synthesis of quantum circuits in Linear Nearest Neighbor model using Positive Davio Lattices”, Facta Univ. Ser.: Elec. Energ., vol. 24, No. 1, April 2011, pp. 73-89
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